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DESIGN OF A SYSTEM SOFTWARE BASED ON A java SOC processor

Journal of Electronics(China) 2010年第6期27卷 853-859页

作者： Chen Zhirui Lin Chunyou Tan Hongzhou School of Information Science and Technology Sun Yat-Sen University Guangzhou 510006 China

java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of java games and other gadgets on mobile platforms, as well as on set-up-box systems. As java applications become more sophisticated, the java Virtual Machine (JVM) mid-dle-wares in embedded systems are not satisfying, java-specific chips extend in the market. All existing java-based system software or Operating System (OS) are used on JVM, they cannot be used on java processors. It is important to develop a pure java system software or OS so that embedded systems using java processors will have great performance in java applications. This paper presents a set of system software designed for a java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to ex-perimental results, the system software provides interfaces for java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for java applications when the system software is implemented.

关键词： java processor Operating System (OS) Task scheduling File management Device management

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Development methodology of ASIP based on java byte code using HW/SW co-design system for processor design

Development methodology of ASIP based on Java byte code usin...

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24th IEEE International Conference on Distributed Computing Systems

作者： Yanagisawa, H Uehara, M Mori, R Toyo Univ Dept Informat & Comp Sci Kawagoe Saitama Japan

ISBN: (纸本)0769520871

To develop an ASIP (Application Specific Instruction set processor), development of HW (hardware) and development of SWDE (software development environments) are required. Separate develops of HW and SWDE in a short time are difficult. So HW/SW co-design system is necessary rapid develop of ASIPs. We have developed C-DASH(C-like Design Automation Shell), which is a HW/SW co-design system for designing processors based on ISA (Instruction Set Architecture). This paper describes the HW/SW co-design system C-DASH, along with a description of a java processor that directly executes java byte code is given as an example.

关键词： H-W/SW codesign system ISA ASIP java processor C-DASH

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A software/hardware cooperated stack operations folding model for java processors

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JOURNAL OF SYSTEMS AND SOFTWARE 2004年第3期72卷 377-387页

作者： Ton, LR Chang, LC Shann, JJ Chung, CP Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu 30050 Taiwan

java has become the most important language in the Internet area, but the execution performance of java processors is severely limited by the true data dependency inherited from the stack architecture defined by Sun's java Virtual Machine. A sequential hardware-based folding algorithm-POC folding model was proposed in the earlier research to eliminate up to 80.1% of stack push and pop bytecodes. The remaining stack push and pop bytecodes cannot be folded due to the sequential checking characteristic of the POC folding model. In this paper, a new software/hardware cooperated folding algorithm-T-POC (Tagged-POC) folding model is proposed to enhance the folding ability of the POC-based java processors to fold the remaining stack push and pop bytecodes. While executing the bytecodes, bytecode grouping and rescheduling are done by a T-POC bytecode rescheduler to generate the new binary class images in memory. With the cooperation of the hardware-based POC folding model, higher execution performance can be achieved by executing the newly generated class images. Statistical data show that 94.8% of stack push and pop bytecodes can be folded, and the overall execution speedups of 2-, 3-, and 4-foldable strategies are 1.72, 1.73 and 1.74, respectively, as compared to a single-pipelined stack machine without folding. (C) 2003 Elsevier Inc. All rights reserved.

关键词： java processor stack operations folding POC folding model T-POC folding model T-POC bytecode rescheduler

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A predecoding technique for ILP exploitation in java processors

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JOURNAL OF SYSTEMS ARCHITECTURE 2008年第7期54卷 707-728页

作者： Sideris, Isidoros Pekmestzi, Kiamal Economakos, George Natl Tech Univ Athens Sch Elect & Comp Engn Athens 15780 Greece

java processors have been introduced to offer hardware acceleration for java applications. They execute java bytecodes directly in hardware. However, the stack nature of the java virtual machine instruction set imposes a limitation on the achievable execution performance. In order to exploit instruction level parallelism and allow out of order execution, we must remove the stack completely. This can be achieved by recursive stack folding algorithms, such as OPEX, which dynamically transform groups of java bytecodes to RISC like instructions. However, the decoding throughputs that are obtained are limited. In this paper, we explore microarchitectural techniques to improve the decoding throughput of java processors. Our techniques are based on the use of a predecoded cache to store the folding results, so that it could be reused. The ultimate goal is to exploit every possible instruction level parallelism in java programs by having a superscalar out of order core in the backend being fed at a sustainable rate. With the use of a predecoded cache of 2 x 2048 entries and a 4-way superscalar core we have from 4.8 to 18.3 times better performance than an architecture employing pattern based folding. (c) 2008 Elsevier B.V. All rights reserved.

关键词： java processor stack folding predecoded cache ILP

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Design of an optimal folding mechanism for java processors

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MICROprocessorS AND MICROSYSTEMS 2002年第8期26卷 341-352页

作者： Ton, LR Chang, LC Shann, JJ Chung, CP Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan Ind Technol Res Inst Comp & Commun Res Labs Hsinchu 310 Taiwan

java has become the most important language in the Internet area, but its execution performance is severely limited by the true data dependency inherited from the stack architecture defined by the Sun's java Virtual Machine (JVM). To enhance the performance of the JVM, a stack operations folding mechanism for the picojava-II processor was proposed by Sun Microsystems to fold 42.3% stack push/pop instructions. A systematic folding algorithm-Producer, Operator, and Consumer (POC) folding model was proposed in the earlier research to eliminate up to 82.9% of stack push/pop instructions. The remaining push and pop instructions cannot be folded due to the sequential checking characteristic of the POC folding model. A new folding algorithm-enhanced POC (EPOC) folding model is proposed in this paper to further fold the remaining push and pop instructions. In the EPOC folding model, stack push/pop instructions are folded with the proposed Stack Reorder Buffer (SROB) architecture. With a small SROB size of 584 bits, almost all of the stack push/pop instructions can be folded with the precise exception handling capability. Statistical data shows that 98.8% of the stack push/pop instructions can be folded, and the average execution performance speedup of a 4-foldable processor with a 7-byte instruction buffer is 1.74 as compared to a traditional single-pipelined stack machine without folding. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： java Virtual Machine stack operations folding POC folding model EPOC folding model java processor

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LOGIC STRUCTURE OF PROGRAMMABLE INSTRUCTIONS FOR java processorS

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Journal of Electronics(China) 2009年第5期26卷 711-714页

作者： Chen Zhirui Tan Hongzhou School of Information Science and Technology Sun Yat-Sen University Guangzhou 510005 China

There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides java systems.

关键词： Programmable instructions java processor System on Chips (SoCs)

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Real-time event-handling and scheduling on a multithreaded java microcontroller

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MICROprocessorS AND MICROSYSTEMS 2003年第1期27卷 19-31页

作者： Kreuzinger, J Brinkschulte, U Pfeffer, M Uhrig, S Ungerer, T Univ Augsburg Inst Comp Sci D-86159 Augsburg Germany Univ Karlsruhe Inst Comp Design & Fault Tolerance D-76128 Karlsruhe Germany Univ Karlsruhe Inst Proc Control Automat & Robot D-76128 Karlsruhe Germany

Our aim is to investigate the suitability of hardware multithreading for real-time event handling in combination with appropriate real-time scheduling techniques. We designed and evaluated a multithreaded microcontroller based on a java processor core. java threads are used as Interrupt Service Threads (ISTs) instead of the Interrupt Service Routines (ISRs) of conventional processors. Our proposed Komodo microcontroller supports multiple ISTs with zero-cycle context switching overhead. A so-called priority manager implements several realtime scheduling algorithms in hardware. We show the feasibility of a hardware real-time scheduler integrated deeply into the processor pipeline with a VHDL design and its synthesis. Evaluations with a software simulator and real-time applications as benchmarks show that hardware multithreading reaches a 1.2-1.4 performance increase for hard real-time applications (multithreading without latency utilization) and a 2.0-2.6 speedup by latency utilization for programs without hard real-time requirements. With respect to real-time scheduling on a multithreaded microcontroller, the Least Laxity First (LLF) scheme outperforms the Fixed Priority Preemptive (FPP), Earliest Deadline First (EDF), and Guaranteed Percentage (GP) schemes, but suffers from the highest implementation costs. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： multithreaded processor java processor multithreaded microcontroller real-time scheduling real-time event handling

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An analytical POC stack operations folding for continuous and discontinuous java bytecodes

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JOURNAL OF SYSTEMS ARCHITECTURE 2002年第1-3期48卷 1-16页

作者： Ton, LR Chang, LC Chung, CP Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan

The execution performance of a stack-based java virtual machine (JVM) is limited by the true data dependency. To enhance the performance of the JVM, a stack operations folding mechanism for the picojava-I/II processor was proposed by Sun Microsystems to fold 42.3% stack operations. By comparing the continuous bytecodes with predefined folding patterns in instruction decoder, the number of push/pop operations in between the operand stack and the local variable could be reduced. In this study, an enhanced POC (EPOC) folding model is proposed to further fold the discontinuous bytecodes that cannot be folded in continuous bytecodes folding mechanisms. By proposing a stack re-order buffer (SROB) to help the folding check processes, the EPOC folding model can fold the stack operations perfectly with a small size of SROB implementation. Statistical data shows that the four-foldable strategy of the EPOC folding model can eliminate 98.8% of push/pop operations with an instruction buffer size of 7 bytes and the SROB size of eight entries. (C) 2002 Elsevier Science B.V. All rights reserved.

关键词： java virtual machine stack operations folding POC folding model EPOC folding model java processor

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Extending an embedded RISC microprocessor for efficient translation based java execution

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MICROprocessorS AND MICROSYSTEMS 2009年第7-8期33卷 415-429页

作者： Sideris, Isidoros Pekmestzi, Kiamal Economakos, George Natl Tech Univ Athens Microprocessors & Digital Syst Lab Sch Elect & Comp Engn Athens 15780 Greece

java has gained great popularity in embedded appliances such as set-top boxes, smart phones and other hand held devices. In this paper we propose a translation based hw/sw codesigned java virtual machine architecture, which extends a typical embedded RISC processor. The architectural extensions we propose include special instructions that accelerate translated blocks dispatch and security checks for arrays and objects. The extensions are done in a way that operating systems support is maintained, something that makes their adoption more attractive. Benchmarking using Embedded Caffeine Mark (ECM) benchmarks, showed significant speedups, especially when high performance RISC processors are employed. (C) 2009 Elsevier B.V. All rights reserved.

关键词： java processor Codesigned virtual machine Embedded java

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Architectural solution to object-oriented programming

Architectural solution to object-oriented programming

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12th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007)

作者： Yiyu, Tan Fong, Anthony S. Xiaojian, Yang Nanjing Univ Technol Coll Informat Sci & Engn 5 Xinmofan Rd Nanjing Peoples R China City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China

ISBN: (纸本)9783540743088

Object-oriented programming has become a major trend in software development for large-scale software systems. However, the classic von Neumann architecture machines have certain limitations for object-oriented computing, such as system security and overhead. To address these limitations, architectural support on object-oriented programming has been introduced. In this paper, an architectural solution to object-oriented programming in a java processor named jHISC is described, where a new object representation model is mapped into hardware directly and the object-oriented programming features is implemented through controlling the related fields in the object context. Moreover, the object representation model is designed to access object information in parallel to speed up object-oriented operation. Compared with Picojava II, JOP, JDK1.5.0_05 interpreter and HotSpot JIT compiler, it has a great improvement on execution of java programs.

关键词： java java processor object-oriented programming

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