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检索条件"主题词=Java processor"

共 46 条记录，以下是31-40 订阅

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Low-Cost Class Caching Mechanism for java SoC

Low-Cost Class Caching Mechanism for Java SoC

引用

International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010)

作者： Hwang, Chien-Feng Su, Kuan-Nian Tsai, Chun-Jen Natl Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (纸本)9781424453092

In this paper, we have presented a low-cost java class caching mechanism for java processors. The design is integrated into a heterogeneous dual-core java SoC that is targeted for embedded multimedia applications with GUI support. The design goal of the proposed caching mechanism is to improve the java program execution performance without the complexity of a multi-way set associative cache. Since object-oriented java programs are usually composed of many small classes, the proposed low-cost caching mechanism works fairly well for practical applications. The java SoC is implemented and emulated on an Xilinx Virtex-4 device and the benchmark results show that the performance of the proposed dual-core java SoC is faster than other popular software-based VMs for embedded systems.

关键词： Embedded systems Heterogeneous dual-core processor java cache java processor

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A Readback Based General Debugging Framework for Soft-Core processors 34

A Readback Based General Debugging Framework for Soft-Core P...

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34th IEEE International Conference on Computer Design (ICCD)

作者： Li, Changgong Schwarz, Alexander Hochberger, Christian Tech Univ Darmstadt Dept Elect Engn & Informat Technol Comp Syst Grp Darmstadt Germany

ISBN: (纸本)9781509051427

Using Field Programmable Gate Arrays (FPGAs) as implementation platform for systems-on-chip (SoC) has become quite popular. Typically, the software part of the system functionality is executed on a soft-core processor. Debugging such systems becomes more difficult than standard SoCs since regular debugging facilities are not always available for the processor cores and also additional hardware problems can overlap with software bugs. Thus, it is interesting to provide a general debugging framework that can help to identify SW and HW problems. In this contribution, we use the readback feature of modern FPGAs to implement such a general framework while at the same time minimizing the additional HW resources required for the debugging. We interface our debugging facilities with a full featured development environment such that the user can work at a very high level of abstraction.

关键词： Hardware debugging soft-core debugging java processor bitstream readback

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An instruction cache architecture for parallel execution of java threads

An instruction cache architecture for parallel execution of ...

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4th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2003)

作者： Chu, WM Li, YM Univ Aizu Dept Comp Hardware Aizu Wakamatsu 9658580 Japan

ISBN: (纸本)0780378407

Designing a java processor supporting horizontal multithreading has been becoming more attractive as network computing gains importance. Different from the traditional superscalar processors that issue multiple instructions from a single instruction stream to exploit the instruction level parallelism (ILP), the horizontal multithreading java processors issue multiple instructions (bytecodes) from multiple threads in parallel to exploit not only the ILP but the thread level parallelism (TLP). Such processors have multiple dispatch slots and require the instruction fetch unit to supply instructions with much higher bandwidth than superscalar processors. Using a traditional superscalar cache architecture in a horizontal multithreading java processor results in high cache miss ratio caused by the interference among the threads. This paper investigates multibank instruction cache architecture for horizontal multithreading java processor to meet the requirements of the high instruction fetch bandwidth. In order to evaluate the cache performance as well as the horizontal multithreading java processor performance, we developed a trace driven simulator. The simulator consists of a trace generator that generates the java bytecode execution traces and an architectural simulator that reads the traces and evaluates,the performance of the instruction cache and the overall performance of the java processor. Our simulation results show that the performance improvements are obtained by the low cache miss ratio and the high instruction fetch bandwidth of the proposed cache architecture. The IPC performance is about 19 when both the number of slots and the number of banks are 8, about 5 times better than one bank cache.

关键词： Cache java virtual machine java processor instruction level parallelism thread level parallelism multithreading performance evaluation trace-driven simulation

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On the Scalability of Time-predictable Chip-Multiprocessing 12

On the Scalability of Time-predictable Chip-Multiprocessing

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10th International Workshop on java Technologies for Real-Time and Embedded Systems (JTRES)

作者： Puffitsch, Wolfgang Schoeberl, Martin Off Natl Etud & Rech Aerosp Dept Modeling & Informat Proc Toulouse France Tech Univ Denmark Dept Informat & Math Modeling Lyngby Denmark

ISBN: (纸本)9781450316880

Real-time systems need a time-predictable execution platform to be able to determine the worst-case execution time statically. In order to be time-predictable, several advanced processor features, such as out-of-order execution and other forms of speculation, have to be avoided. However, just using simple processors is not an option for embedded systems with high demands on computing power. In order to provide high performance and predictability we argue to use multiprocessor systems with a time-predictable memory interface. In this paper we present the scalability of a java chip-multiprocessor system that is designed to be time-predictable. Adding time-predictable caches is mandatory to achieve scalability with a shared memory multi-processor system. As java bytecode retains information about the nature of memory accesses, it is possible to implement a memory hierarchy that takes the characteristics of different types of accesses into account. For tasks with low communication the measured speedup of this time-predictable system is in the range of 6 to 7 for eight processor cores, compared to execution on a single-core processor.

关键词： Time-predictable computer architecture java processor

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Secure, real-time and multi-threaded general-purpose embedded java microarchitecture

Secure, real-time and multi-threaded general-purpose embedde...

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10th Euromicro Conference on Digital System Design

作者： Zabel, Martin Preusser, Thomas B. Reichel, Peter Spallek, Rainer G. Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9780769529783

This paper presents a novel implementation of an embedded java microarchitecture for secure, real-time, and multi-threaded applications. A general-purpose platform is established through the support of modern features of object-oriented languages, such as exception handling, automatic garbage collection and interface types. New techniques have been implemented for specific real-time issues, such as an integrated stack and thread management for fast context switching, concurrent garbage collection for real-time threads and autonomous control flows through preemptive round-robin scheduling.

关键词： real-time multi-threading garbage collection embedded system general-purpose java processor

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Performance Gain of a Data Flow Oriented ISA as Replacement for java Bytecode 34th

Performance Gain of a Data Flow Oriented ISA as Replacement ...

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34th International Conference on Architecture of Computing Systems (ARCS)

作者： Schwarz, Alexander Hochberger, Christian Tech Univ Darmstadt Merckstr 25 D-64283 Darmstadt Germany

ISBN: (纸本)9783030816827;9783030816810

java Bytecode is used as binary format for a number of programming languages and programming systems. Since java virtual machines exist for many platforms, it can be regarded as a universal execution format. Consequently, several hardware implementations of Bytecode processors exist. Unfortunately, they all suffer from the inefficiencies of the Bytecode principle. Particularly, the operand stack and the local variable storage are bottlenecks during execution. In this contribution, we evaluate the performance gain that can be achieved by replacing Bytecode with a data flow oriented instruction set architecture (ISA). We describe the changes that are necessary to adapt an existing Bytecode processor to the new ISA. Ultimately, we compare execution times and HW resources for both processors, which are based on identical ALUs and heap memory model. Execution times are evaluated using the SPEC JVM98 benchmark and a set of micro benchmarks which have a very flat call graph. SPEC JVM98 reaches a speedup of 1.76 and the micro benchmarks even gain a factor of 2.80.

关键词： Instruction set architecture Microarchitecture Self-timed java processor Online synthesis

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Engineering an Optimized Instruction Set Architecture for AMIDAR processors 33rd

Engineering an Optimized Instruction Set Architecture for AM...

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33rd International Conference on Architecture of Computing Systems (ARCS)

作者： Schwarz, Alexander Hochberger, Christian Tech Univ Darmstadt Merckstr 25 D-64283 Darmstadt Germany

ISBN: (纸本)9783030527938;9783030527945

Newly developed instruction set architectures are nowadays typically based on the RISC principle. Yet, more abstract instruction sets also have their advantages. In the AMIDAR project java Bytecode was used as the instruction set. Instructions are realized as compositions of micro instructions that are distributed to specialized functional units. An explicit timing of these micro instructions is not necessary in AMIDAR processors. This simplifies the conversion of compute intense instruction sequences into hardware structures while the system is running. The relatively high abstraction level of the Bytecode facilitates the analysis and synthesis remarkably. Yet, the native execution of the Bytecode comes with a number of drawbacks. In this contribution, we show a new instruction set architecture that preserves the high abstraction level of Bytecode while at the same time avoiding inefficient data transports. We show that on average the new instruction set reduces the number of clock cycles for our benchmark set by a factor of 3.

关键词： Instruction set architecture Microarchitecture Self-timed java processor Online synthesis

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An IP core for embedded java systems

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International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation

作者： Uhrig, Sascha Mische, Joerg Ungerer, Theo Univ Augsburg Inst Comp Sci D-86159 Augsburg Germany

ISBN: (纸本)9783540736226

This paper proposes a multithreaded java processor as an IP core for Altera's System-on-Programmable-Chip environment. The processor core is an enhancement of the earlier developed multithreaded java processor named Komodo. It features a real-time capable garbage collection and integrated real-time scheduling schemes. Hence, it is suitable for embedded hard, soft, and non real-time systems. The facts that the processor is designed as an IP core and that it is a special java processor makes both easier: hardware design and software development.

关键词： implantable systems embedded system-on-a-chip implementations multithreaded processors embedded operating systems real-time embedded systems java processor

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A scheduling technique providing a strict isolation of real-time threads 7

A scheduling technique providing a strict isolation of real-...

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7th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2002)

作者： Brinkschulte, U Kreuzinger, J Pfeffer, M Ungerer, T Univ Karlsruhe Inst Comp Design & Fault Tolerance D-76128 Karlsruhe Germany

ISBN: (纸本)0769515762

Highly dynamic programming enviromnents for embedded real-time systems require a strict isolation of real-time threads from each other to achieve dependable systems. We propose a new real-time scheduling technique, called guaranteed percentage (GP) scheme that assigns each thread a specific percentage of the processor power A hardware scheduler in conjunction with a multithreaded processor guarantees the execution of instructions of each thread according to their assigned percentages within a time interval of 100 processor cycles. We compare performance and implementation overhead of GP scheduling against fixed priority preemptive (FPP), earliest deadline first (EDF), and least laxity first (LLF) scheduling using several benchmarks on our Komodo microcontroller that features a multithreaded java processor kernel. Our evaluations show that GP scheduling reaches a speed-up similar to EDF and FPP but worse than LLF However;its hardware implementation costs are still reasonable, whereas the LLF overhead is prohibitive. Only GP reaches the isolation goal among the examined scheduling schemes.

关键词： real-time scheduling performance analysis timing isolation multithreaded processor java processor guaranteed percentage scheduling

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VHDL vs. Bluespec System Verilog: A case study on a java embedded architecture 08

VHDL vs. Bluespec System Verilog: A case study on a Java emb...

引用

23rd Annual ACM Symposium on Applied Computing

作者： Gruian, Flavius Westmijze, Mark Lund Univ Dept Comp Sci S-22100 Lund Sweden Univ Twente Dept Comp Sci Enschede Netherlands

ISBN: (纸本)9781595937537

This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a java embedded architecture, comprising a java native processor and a memory management unit. The processor is a micro-programmed, pipelined, java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.

关键词： java processor embedded systems Bluespec

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