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A robust stack folding approach for java processors: an operand extraction-based algorithm

JOURNAL OF SYSTEMS ARCHITECTURE 2001年第8期47卷 697-726页

作者： El-Kharashi, MW Elguibaly, F Li, KF Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada

Data dependency in stack operations limits the performance of java processors. To enhance java's performance, existing literature suggests using stack operations folding. We extend this concept in a new folding algorithm that identifies principle operations in folding groups and extracts necessary operands from the bytecode queue. The proposed algorithm permits nested pattern folding and multiple issue of folding groups. Hence, the need for and therefore the limitations of a stack are eliminated. This paper discusses various aspects of the proposed algorithm and illustrates different folding scenarios as well as possible hazards. Benchmarking using SPECjvm98 shows excellent performance gains as compared to existing algorithms. (C) 2001 Elsevier Science B.V. All rights reserved.

关键词： java java virtual machine java processors java performance java bytecode folding stack processors

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Stack operations folding in java processors

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1998年第5期145卷 333-340页

作者： Chang, LC Ton, LR Kao, MF Chung, CP Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu 30050 Taiwan

Traditionally, the performance of a stack machine has been limited by the true data dependency. A performance enhancement mechanism, stack operations folding, was used in Sun Microelectronics' picojava-I design, and it can fold up to 60% of all stack operations. The authors use the java bytecode language as the target machine language, and study java instruction folding on a proposed folding model, the POC model, which is used to illustrate the theoretical folding operations. Various practical folding strategies based on the POC model are introduced and evaluated. Statistical data show that the 4-foldable strategy eliminates 84% of all stack operations, and the 2-, 3-, and 4-foldable strategies result in overall program speedups of 1.22, 1.32 and 1.34, respectively, as compared to a stack machine without folding. Furthermore, the 4-foldable strategy is the most practical and cost effective of a java stack machine design with a decoder width of 8 bytes. Circuit simulation results show that a 100MHz 4-foldable folding mechanism can be realized with 0.6 mu m CMOS standard cells, or 240MHz with 0.251 mu m CMOS technology.

关键词： java processors stack machines

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A quantitative study for java microprocessor architectural requirements. Part I: Instruction set design

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MICROprocessors AND MICROSYSTEMS 2000年第5期24卷 225-236页

作者： El-Kharashi, MW ElGuibaly, F Li, KF Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada

java was designed for network programming. This imposes certain requirements on its virtual machine instruction set architecture and on designs that support java. The purpose of this study is to carry out a behavioral analysis of the different aspects of java instruction set architecture. This will help in establishing the hardware requirements for executing java bytecodes. First, the bytecode interpreter was instrumented to include performance counters and statistics collectors. Then performance metrics were collected through benchmarking. Analyzing these data helps to identify performance-critical aspects that are candidates for hardware support, while less critical aspects can be left for software implementations. In this first part of our two-part paper, we study access patterns for data types, addressing modes, and instruction encoding. Recommendations for architectural requirements for java processors will be made throughout this study. (C) 2000 Elsevier Science B.V. All rights reserved.

关键词： java java virtual machine java instruction set architecture java processors

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The JAFARDD processor: A java Architecture based, on a folding algorithm, with reservation stations, dynamic translation, and dual processing

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2002年第4期48卷 1004-1015页

作者： El-Kharashi, MW Gebali, F Li, KF Zhang, F Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 2Y2 Canada

This paper presents the JAFARDD (a java Architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing) processor. JAFARDD dynamically translates java stack-dependent bytecodes to RISC-style stack-independent instructions to facilitate the use of a general-purpose RISC core. JAFARDD enables the exploitation of instruction level parallelism among the translated instructions by the use of bytecode folding coupled with Tomasulo's algorithm. We detail the JAFARDD architecture and the global architecture design principles observed while designing each pipeline module. We also illustrate the flow of the java bytecodes through each of the processing phases. Benchmarking of JAFARDD using SPECjvm98 has shown a performance improvement between 1.10 and 2.25.

关键词： reservation stations Tomasulo's algorithm dynamic scheduling java java virtual machine java processors java bytecode folding stack processors local variable renaming instruction shelving dual processing

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Hardwiring the OS Kernel into a java Application Processor 28

Hardwiring the OS Kernel into a Java Application Processor

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28th IEEE International Conference on Application-specific Systems, Architectures and processors (ASAP)

作者： Tsai, Chun-Jen Lin, Cheng-Ju Chen, Cheng-Yang Lin, Yan-Hung Ji, Wei-Jhong Hong, Sheng-Di Natl Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (纸本)9781509048250

This paper presents the design and implementation of a hardwired OS kernel circuitry inside a java application processor to provide the system services that are traditionally implemented in software. The hardwired system functions in the proposed SoC include the thread manager, the memory manager, and the I/O subsystem interface. There are many advantages in making the OS kernel a hardware component, such as a fast system boot time, highly efficient single-core multi-thread context-switching performance, and a better potential for supporting a complex multi-level memory subsystem. In addition, since the target application processor used in this paper is based on a java processor, the system is not susceptible to the stack and pointer-based security attacks that are common to the register-based processors. Full-system performance evaluations on an FPGA show that the proposed system is very promising for deeply-embedded multi-thread applications.

关键词： Hardware thread mangers Hardware memory managers java processors Embedded application processors

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JAIP-MP: A Four-Core java Application Processor for Embedded Systems 1

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23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Tsai, Chun-Jen Wu, Tsung-Han Su, Hung-Cheng Chen, Cheng-Yang Natl Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (数字)9783319460970

ISBN: (纸本)9783319460970;9783319460963

In this chapter, we present a four-core java application processor, JAIP-MP. In addition to supporting multi-core coherent data accesses to shared memory, each processor core in JAIP-MP is a hardwired java core that is capable of dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method/object caching, java exception handling, preemptive multi-threading, and memory management. Most of the essential OS kernel functions are implemented in hardware. In particular, the preemptive multi-threading performance is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. Currently, single-cycle context switching with a time quantum as small as 20 mu s can be achieved by each core. More importantly, the java language model itself makes it possible to maintain binary portability of application software regardless of the hardwired OS kernel component. In summary, JAIP-MP could be used to study the potential benefits of OS kernel implementation in hardware.

关键词： java processors Multi-core processors Embedded SoC Hardwired operating system kernel

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Reduzindo o consumo de energia em MPSoCs heterogêneos via clock gating

Reduzindo o consumo de energia em MPSoCs heterogêneos via c...

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作者： Motta, Rodrigo Bittencourt

In this work we present an architecture that enables the generation of bus-based, scalable heterogeneous Multiprocessor Systems-on-Chip (MPSoCs), supporting different memory organizations. Intertask communication is specified by means of a shared memory structure that assures collision avoidance and promotes energy savings through a dynamic clock gating triggering. We also introduce a Dynamic Core Freezing (DCF) technique, which boosts energy savings taking advantage of processor idle cycles during memory accesses. Moreover, the combination of the memory organizations enables the architecture to exploit easy task migration by means of the task context saving in the shared data memory. Moreover, we show the high-level simulator, based on the proposed architecture, created in order to extract the energy savings enabled with the clock gating and the DCF techniques. The simulator accepts as input execution trace files of java applications, from which it generates a new file that contains the mapping of the instructions found in the trace file for different instruction classes. This way, we can model different processor architectures, using the mapping file to simulate the MPSoC. Also, the simulator enables us to experiment with different memory organizations to estimate their impact on the executed instructions, bus contention, and energy consumption. As case study we have modeled different versions of a java processor in order to experiment with different execution patterns over different memory organizations. Experiments based on a synthetic application running on an MPSoC containing different versions of a java processor show a large improvement in energy efficiency with a minimal area cost. Besides that, we also present experiments based on applications of the SPECjvm98 benchmark, which show the impact on the energy efficiency when we change the application type. Moreover, the experiments show a huge improvement in the energy efficiency when applying the DCF techni

关键词： Microeletrônica Clock gating Heterogeneous MPSoCs Sistemas embarcados SoC java processors Embedded systems Dissertação

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