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Optimizing FIR Filter Efficiency with Advanced Hybrid Multiplier Techniques

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2025年第6期34卷

作者： Rao, E. Jagadeeswara Mercy, M. Grace Kumar, K. Jayaram Rajanbabu, M. Ramya, K. Sudha Gayatri Vidya Parishad Coll Engn Autonomous Dept Elect & Commun Engn Visakhapatnam Visakhapatnam Andhra Pradesh India GITAM GITAM Sch Technol Dept Elect Elect & Commun Engn Visakhapatnam Andhra Pradesh India Aditya Coll Engn & Technol Dept Elect Elect & Commun Engn Surampalem Andhra Pradesh India Lendi Inst Engn & Technol Dept Elect Elect & Commun Engn Vizianagaram Andhra Pradesh India Govt Polytech Women Dept Elect & Instrumentat Engn Srikakulam Andhra Pradesh India

In modern signal processing applications, Finite Impulse Response (FIR) filters are extensively used in various domains such as communications, consumer electronics and audio systems. Multiplication plays a pivotal role in implementing numerous algorithms, making the selection of a fast and efficient multiplier critical for FIR filters. With the growing demand for power-efficient algorithms, the need for advanced multipliers capable of handling large numerical inputs without compromising the performance has become evident. Therefore, this paper introduces a novel approach to tackle the challenges associated with large-scale multiplication in FIR filters by drawing inspiration from ancient Indian mathematical techniques known as Vedas. Specifically, a Vedic Multiplier (VM) is presented that harnesses the power of distinct Vedic sutras, enabling efficient multiplication operations. To further enhance performance, the karatsuba algorithm (KA) and two additional sutras are integrated, such as Urdhva Tiryagbhyam (UT) and Nikhilam Sutra (NS), to form a hybrid multiplier. Furthermore, all proposed multipliers are implemented, along with existing designs, in Verilog code using Xilinx Vivado and Cadence Genus. In addition, the experimental results show that the proposed designs outperform the existing designs in terms of area, power consumption and delay. By significantly reducing the multiplier delay and power consumption, the proposed designs offer a promising solution for addressing the challenges of large-scale multiplication in FIR filter designs.

关键词： FIR filter karatsuba algorithm Vedic sutras Xilinx Vivado tool

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Integration in CNN and FIR filters for improved computational efficiency in signal processing

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AIN SHAMS ENGINEERING JOURNAL 2025年第1期16卷

作者： Sridevi, A. Sathiya, A. M Kumarasamy Coll Engn Autonomous Dept Elect & Commun Engn Karur 639113 Tamil Nadu India

This research paper explains the design process of the 8 x 8 Vedic multipliers based on the "UrdhvaTiryagbhyam" Sutra in combination with the "Nikhilam Sutra" and the karatsuba algorithm. To effectively generate a 16-bit product, the used architecture consists of four four-by-four Vedic modules, an 8:1 carry-save adder, and two nine-bit binary adders. The UrdhvaTiryagbhyam approach splits multiplications into pieces, the Nikhilam Sutra uses the concept of binary complements, and the karatsuba algorithm offers improvements in large numbers of multiplications. The proposed addition microarchitecture, which consists of using a Fast Carry Switching Adder and the Kogge-Stone Adder with associated selection signals and speculative logic, improves carry propagation time. The ability of the Vedic multiplier is tested within an FIR filter and a CNN processing element, revealing significant enhancements in speed and efficiency. Importantly, the proposed multiplier based on the modification of Vedic Nikhilam yields the lowest power consumption (248.93 mW), the lowest delay (27.95 ns), and the lowest PDP (6.96 pJ), thus making it appropriate for usage in HPC related to signal processing and neural network computations. Moreover, the developed FIR filter for the CNN and the EEG signal datasets were employed to detect seizures and Alzheimer's disease. The incorporation of the Vedic multiplier into the CNN framework reveals the application of the proposed idea in the field of biomedical signal processing with improved computational speed and accuracy. The results corroborate the multiplier's efficiency in decreasing the computational complexity and enhancing the possibility of real-time analysis of CNN-based systems in healthcare.

关键词： FIR filter CNN Nikhilam Sutra karatsuba algorithm Filter coefficient Fast Carry Switching Adder Kogge-Stone Adder

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Design of energy efficient N-bit vedic multiplier for low power hardware architecture

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INTERNATIONAL JOURNAL OF ELECTRONICS 2025年第7期112卷 1417-1437页

作者： Sridevi, A. Sathiya, A. M Kumarasamy Coll Engn Dept Elect & Commun Engn Karur 639113 Tamil Nadu India

In this paper, we introduce an advanced design of an N-bit Vedic multiplier using Nikhilam Sutra and karatsuba algorithms, tailored for low power hardware architectures. Our approach innovatively combines these ancient mathematical techniques to significantly enhance computational efficiency in digital systems. The primary novelty of our method lies in its capability to drastically reduce both power consumption and operational delay. Compared to conventional multipliers, our design demonstrates an average area reduction of 56% and a latency reduction of 45%. Additionally, the integration of the karatsuba algorithm optimises the structural design of the multiplier, further lowering the requirements for computational units. This dual-sutra approach not only optimises energy efficiency but also enhances overall effectiveness, making it highly suitable for image and signal processing as well as biomedical applications where power efficiency is crucial. By explicitly stating these key advancements, we aim to clearly communicate the significant strides our research has made in the field of energy-efficient hardware design.

关键词： Nikhilam sutra karatsuba algorithm computational complexity bit reduction N-bit multiplier

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Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2022年第10期94卷 1067-1082页

作者： Huai, Zheang Zhou, Jingbo Zhang, Xinmiao Ohio State Univ Columbus OH 43210 USA

Modular multiplication of long integers is a key component of elliptic curve cryptography and homomorphic encryption. The multiplication complexity can be reduced by applying the karatsuba algorithm that decomposes the operands into shorter segments. Nevertheless, for long numbers, it takes many clock cycles in previous designs to calculate the final result by adding the segment products and then carrying out modular reduction. This paper considers Solinas prime moduli and proposes to integrate modular reduction into the segment products computed in the karatsuba multiplication process. Accordingly, the intermediate results become much shorter and they can be added simultaneously using a Wallace-tree-based multi-input adder with small area overhead. Moduli of different formats are investigated in this paper. In addition, various optimization schemes are proposed to further reduce the latency and area requirement. Complexity analysis shows that, for 2, 3 and 4 decomposed multiplication with an example modulus, our design on average achieves 18.5% reduction on the latency with 5.5% increase in the area compared to the design that carries out modular reduction after final result of the multiplication is computed.

关键词： Carry-save adder Generalized Mersenne prime karatsuba algorithm Modular multiplication Solinas prime Wallace tree

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Design and Evaluation of Finite Field Multipliers Using Fast XNOR Cells 23

Design and Evaluation of Finite Field Multipliers Using Fast...

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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Patwari, Nitin D. Srivastav, Anjul Kabra, Mayank Jonna, Prashant Rao, Madhav IIIT Bangalore Bangalore Karnataka India

ISBN: (纸本)9798400701252

The current polynomial multiplication is built on conventional CMOS cells, and no major changes are explored in the standard cell library to improve the performance. Hence state-of-the-art (SOTA) finite field multipliers of operand sizes ranging from 93 to 409 bits were designed and evaluated by adopting faster XNOR cells. The hardware metrics in the form of gates usage, and propagation delay were compared. The SOTA multipliers of different approaches including Conventional algorithm (CA), karatsuba algorithm (KA), Overlap free karatsuba algorithm (OKA), and Overlap-free based multiplication strategy (OBS) were designed and synthesized through ASIC flow using 45 nm GPDK library files. The fast XNOR cell adopted SOTA multipliers improved the compute delay in the range of 8.24% to 33.45%, 8% to 37.05%, 4.63% to 18.36%, and 1.01% to 38.73% for OKA, OBS, CA, and KA respectively. All the design files are made freely available for further usage to research and designers' community.

关键词： Finite Field Multiplier karatsuba algorithm Overlap free karatsuba Standard Cell library Polynomial Multiplication

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Area-Efficient Finite Field Multiplication Using Hybrid SET-MOS Technology

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第11期69卷 4358-4366页

作者： Zhang, Chen Wu, Huapeng Chen, Chunhong Univ Windsor Dept Elect & Comp Engn Windsor ON N9B 3P4 Canada

Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts.

关键词： Single electron transistor finite field multiplier multi-input XOR gate karatsuba algorithm

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Performance Analysis of karatsuba Multiplication algorithm for Different Bit Lengths

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Procedia - Social and Behavioral Sciences 2015年 195卷 1860-1864页

作者： Can Eyupoglu Istanbul Commerce University Faculty of Engineering and Design Department of Computer Engineering Istanbul Turkey

In computer arithmetic, multiplication is one of the most significant operations. Multiplication is used in many operations such as division, squaring and computing reciprocal. In addition, the efficiency of multiplication is crucial due to the use of digital signal processing applications such as correlation, filtering, frequency analysis and image processing. karatsuba algorithm is one of the algorithms developed for increasing the efficiency and reducing the cost in order to simplify multiplication. In this study, the performance of karatsuba algorithm is analyzed in terms of the number of multiplication and the total process time for different bit lengths.

关键词： Computer Arithmetic Multiplication karatsuba algorithm

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High-performance unified modular multiplication algorithm and hardware architecture over G(2m)

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INTEGRATION-THE VLSI JOURNAL 2024年 96卷

作者： Zhao, Shilei Hu, Diankun Liu, Zhiwei Yu, Bin Huang, Hai Ma, Chao Harbin Univ Sci & Technol Harbin Peoples R China

The finite field Modular Multiplier (MM) over GF (2m) based on the National Institute of Standards and Technology (NIST) recommended polynomials can be used as a critical component in many cryptosystems. But much of the research suffers from the problems of only supporting a single curve or being very inefficient. In this paper, we present a KA-based unified algorithm (hybrid field size) and its corresponding architecture for highperformance implementation of the systolic modular multiplier over GF (2m), which can support all the NIST recommended polynomials. A number of efficient techniques have been explored and used to realize a highperformance implementation of the multiplier. First, we propose a three -term KA based MM approach and make it fit for systolic implementation. Second, we propose a configurable, unified irreducible polynomial that can support all five curves recommended by NIST and the corresponding modular reduction method. Third, the corresponding systolic structure is also designed in accordance with (1) and (2) to improve efficiency, and we adopt register sharing and computation unit sharing methods to reduce the space complexity of the proposed structure. Additionally, parallel computation of two163-width MMs is employed to improve resource utilization further. From the synthesis results on ASIC, it is shown that the proposed multipliers have significantly lower latency and higher performance than the existing designs. e.g., the proposed structure could achieve up to a 73 % reduction in area -delay product (ADP) over the existing structures.

关键词： Modular multiplier karatsuba algorithm NIST polynomials Systolic structure

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Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF(2^m) using Hankel matrix and karatsuba algorithm

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IET INFORMATION SECURITY 2013年第2期7卷 75-86页

作者： Hua, Ying Yan Lin, Jim-Min Chiou, Che Wun Lee, Chiou-Yng Liu, Yong Huan Tongji Univ Coll Elect & Informat Engn Shanghai 201804 Peoples R China Feng Chia Univ Dept Informat Engn & Comp Sci Taichung 407 Taiwan Ching Yun Univ Dept Comp Sci & Informat Engn Chungli 320 Taiwan

Multiplication is one important finite field arithmetic operation in cryptographic computations. Dual basis multipliers over Galois field GF(2(m)) have been widely applied in this kind of computations because of its advantage of small chip area. Nevertheless, up to date, there are only few methods that can keep balance of low space complexity and low time complexity at the same time. In order to achieve such an efficient aim, this study presents a novel digit-serial dual basis multiplier that is different from existing ones with a modified cut-set method using karatsuba algorithm as well as Hankel matrix. As a result, the proposed multiplier can save much space and thus be particularly suitable for some hand held devices equipped with only limited resources. The proposed digit-serial dual basis multiplier saves 55% space complexity as compared with existing similar studies with National Institute of Standards and Technology (NIST) suggested values for elliptic curve cryptosystem.

关键词： computational complexity Galois fields Hankel matrices public key cryptography low space complexity digit serial dual basis systolic multiplier Galois field GF(2m) Hankel matrix karatsuba algorithm finite field arithmetic operation cryptographic computations cut set method elliptic curve cryptosystem computational complexity Galois fields Hankel matrices public key cryptography low space complexity digit serial dual basis systolic multiplier Galois field GF(2m) Hankel matrix karatsuba algorithm finite field arithmetic operation cryptographic computations cut set method elliptic curve cryptosystem

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Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime

Efficient Architecture for Long Integer Modular Multiplicati...

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35th IEEE Workshop on Signal Processing Systems (IEEE SiPS)

作者： Huai, Zheang Parhi, Keshab K. Zhang, Xinmiao Ohio State Univ Columbus OH 43210 USA Univ Minnesota Minneapolis MN USA

ISBN: (纸本)9781665401449

Modular multiplication of very long integers is a key building block of fully homomorphic encryption and elliptic curve cryptography. The karatsuba algorithm reduces the multiplication complexity by decomposing the operands into shorter segments. However, in the case of long numbers, adding up the segment products to derive the final product and then carrying out modular reduction as in previous designs can take many clock cycles. This paper focuses on moduli in the format of Solinas prime and proposes to integrate modular reduction into every segment product of the karatsuba integer multiplication. As a result, the length of the intermediate results is further reduced and they can be added up simultaneously by using a carry-save adder at the cost of small area increase. Additionally, the computation scheduling are optimized to reduce the required number of registers and multiplexers. Complexity analysis shows that, for decomposition factors of 2, 3 and 4, our design requires on average 18.5% less clock cycles with only 5.9% area overhead and similar critical path compared to carrying out the modular reduction on the final product.

关键词： Carry-save adder karatsuba algorithm Modular multiplication Solinas Prime

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