Low temperature polycrystalline silicon thin film transistor (LTPS TFT) has a wide application prospect in flat panel display and other fields due to its higher carrier mobility and better conductivity. Motivated with...
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Low temperature polycrystalline silicon thin film transistor (LTPS TFT) has a wide application prospect in flat panel display and other fields due to its higher carrier mobility and better conductivity. Motivated with the development of flat-panel display devices targeting higher resolution, it is imperative to carry out research in small-sized LTPS TFT technology. When the channel size is decreased to a certain extent, the effect of the gradual channel approximation is no longer valid. As a result, the short channel effect and the hot carrier effect will have significant impacts on the LTPS TFT devices. To alleviate and eventually to eliminate these two effects, we introduce and implement the Lightly Doped Drain (ldd) structure in the LTPS TFT device. ldd is a technology by adding lightly doped region between source and drain in a TFT, its series resistance is increased, thereby greatly reducing the electric field of drain, resulting in much less hot carrier effect and short channel effect. However, the introduction of ldd structure might have some adverse impacts on the characteristics of LTPS TFT if not optimized. In this paper, we studied the influence of different ldd structures on TFT performance, finding out the optimal ldd structure.
A lightly doped drain (ldd) region, particularly a gate-overlapped ldd (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new ext...
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A lightly doped drain (ldd) region, particularly a gate-overlapped ldd (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new extraction method for determining the intrinsic characteristics of ldd MOSFETs using a simple series resistance model, in which the GOLD region is assumed to be a depletion MOSFET with a negative threshold voltage derived from C-V measurement. Polycrystalline-silicon (poly-Si) TFTs with a channel length of 4-100mum were used for the test ldd samples, particularly GOLD MOSFETs. It was demonstrated that the new proposed method precisely extracts the intrinsic characteristics of poly-Si GOLD TFTs by comparing them with the intrinsic characteristics of poly-Si Self-Aligned (SA) TFTs extracted by the conventional method.
We propose a metal oxide semiconductor field-effect transistor (MOSFET) whose channel size can be modified by applying control voltage. The variable-channel-size MOSFET (VS-MOS) has a control gate between the main gat...
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We propose a metal oxide semiconductor field-effect transistor (MOSFET) whose channel size can be modified by applying control voltage. The variable-channel-size MOSFET (VS-MOS) has a control gate between the main gate and the source/drain. The control gate possesses a gap at its end in the active region. Owing to this unique layout, the VS-MOS achieves continuous modulation of effective channel size and can be fabricated using the conventional complementary MOS (CMOS) fabrication process. Results of test device fabrication show that the channel size modulation can be enhanced by employing the lightly doped drain (ldd) structure. It is also shown that the logic threshold can he controlled in a CMOS inverter composed of the VS-MOS.
We propose a metal oxide semiconductor field-effect transistor (MOSFET) whose channel size can be modified by applying control voltage. The variable-channel-size MOSFET (VS-MOS) has a control gate between the main gat...
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We propose a metal oxide semiconductor field-effect transistor (MOSFET) whose channel size can be modified by applying control voltage. The variable-channel-size MOSFET (VS-MOS) has a control gate between the main gate and the source/drain. The control gate possesses a gap at its end in the active region. Owing to this unique layout, the VS-MOS achieves continuous modulation of effective channel size and can be fabricated using the conventional complementary MOS (CMOS) fabrication process. Results of test device fabrication show that the channel size modulation can be enhanced by employing the lightly doped drain (ldd) structure. It is also shown that the logic threshold can he controlled in a CMOS inverter composed of the VS-MOS.
Design rules are presented for the suppression of photocurrents generated in the depletion layers of the channel/drain junction regions of low-temperature poly-Si thin-film transistors (TFTs). Device simulation based ...
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Design rules are presented for the suppression of photocurrents generated in the depletion layers of the channel/drain junction regions of low-temperature poly-Si thin-film transistors (TFTs). Device simulation based on modeling the behavior of the density of states in a low-temperature poly-Si TFT was used to find the width of the junction depletion layer. These simulations show that in order to suppress photocurrents to below 6 pA, the ldd region must have a sheet resistance in the range of 30 and 70 kOmega/square, which forces its length to exceed 1 mum. (C) 2003 Wiley Periodicals, Inc.
A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technolo...
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ISBN:
(纸本)0819434787
A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical ldd processing was also developed to improve the short channel effects. The transistor with channel length below 0.1 mu m has normal characteristics at room temperature, a >6V Bvdss, and a transconductance with value as high as in the conventional planar transistor of the same channel length.
作者：
Terada, KMemberFaculty of Information Sciences
Hiroshima City University Hiroshima Japan 731–31 Received his B.E. degree from Waseda University
Tokyo Japan in 1971 and his M.S. and Dr. of Eng. degrees from Kyoto University Kyoto Japan in 1973 and 1989 respectively. In 1973 he joined Central Research Laboratories NEC Corporation Kawasaki Japan where he was first engaged in the measurement of Si-MOSFETs and the development of silicon gate DMOS fabrication process. From 1976 to 1992 he was engaged in the research and development of MOSFETs and MOS memories at Microelectronics Research Laboratories NEC Corporation Sagamihara Japan. During this period he worked on new DRAM cell structures their fabrication processes and MOSFET designs. From 1992 to 1994 he was a research manager of basic LSI process group in Microelectronics Research Laboratories NEC Corporation Tsukuba Japan. Since 1994 he has been with Hiroshima City University where at present he is a Professor on the Faculty of Computer Sciences. Dr. Terada is a member of the Institute of Electronics Information and Communication Engineers of Japan the Japan Society of Applied Physics and the IEEE Electron Devices Society.
To evaluate the accuracy of the effective channel-length extraction method;the behavior of the measurement errors in the least-square method, used twice in the extraction procedure, is studied. It is found that the in...
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To evaluate the accuracy of the effective channel-length extraction method;the behavior of the measurement errors in the least-square method, used twice in the extraction procedure, is studied. It is found that the increased number of data are mainly effective in suppressing the dispersion of the measurement data;these data are also somewhat effective in reducing the actual measurement errors. Based on this result, the actual effective channel-length extraction using experimental MOSFET data is studied. It is observed in the samples used here that the linear relation between total MOSFET resistance and design channel length changes in short channel region. It is found in such a case that as many reference MOSFETs as possible, including both short and long MOSFETs, should be used.
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