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IEEE Information Theory Workshop

作者： Schaefer, A Moerz, M Hagenauer, J Sridharan, A Costello, DJ Tech Univ Munich Inst Commun Engn Munich Germany

ISBN: (纸本)0780377990

We present an analog rotating ring decoder for decoding an ldpc convolutional code. The decoder architecture uses a window of soft received L-values K time units in the past and K time units in the future to decode a given bit. The window of 2K + 1 time units is arranged in a ring structure, and decoding proceeds in a continuous fashion by rotating around the ring. Simulation results indicate performance almost identical to that achieved with digital decoding.

关键词： decoding convolutional codes parity check codes channel coding analogue processing circuits analog rotating ring decoder ldpc convolutional code ldpc code soft received L-values digital decoding channel codes analog transistor circuits belief convolutional coding Channel coding analogue processing circuits DECODING parity check codes low density parity check codes Beliefs Unit of time ROTATING RINGS decoders

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Capacity-Approaching TQC-ldpc convolutional codes Enabling Power-Efficient Decoders

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IEEE TRANSACTIONS ON COMMUNICATIONS 2017年第1期65卷 1-13页

作者： Pisek, Eran Rajan, Dinesh Abu-Surra, Shadi Cleveland, Joseph R. PHAZR Inc Allen TX 75002 USA Southern Methodist Univ Dallas TX 75205 USA

In this paper, we develop a new capacityapproaching code, namely, parallel-concatenated (PC)-Low Density Parity Check (ldpc) convolutional code that is based on the parallel concatenation of trellis-based quasi-cyclic ldpc (TQCldpc) convolutional codes. The proposed PC-ldpc convolutional code can be derived from any QC-ldpc block code by introducing the trellis-based convolutional dependency to the code. The capacity-approaching PC-ldpc convolutional codes are encoded through parallel concatenated trellis-based QC recursive systematic convolutional (RSC) encoder (namely, QCRSC encoder) that is also proposed in this paper. The proposed PC-ldpc convolutional code and the associated encoder retain a fine input granularity on the order of the lifting factor of the underlying block code. We also describe the corresponding trellisbased QC maximum a posteriori probability (namely, QC-MAP) decoder that efficiently decodes the PC-ldpc convolutional code. Performance and hardware implementation results show that the PC-ldpc convolutional codes with the QC-MAP decoder have two times lower complexity for a given bit-error-rate (BER), signal-to-noise ratio, and data rate, than conventional QC-ldpc block codes and ldpc convolutional codes. Moreover, the PC-ldpc convolutional code with the QC-MAP decoder outperforms the conventional QC-ldpc block codes by more than 0.5 dB for a given BER, complexity, and data rate and approaches Shannon capacity limit with a gap smaller than 1.25 dB. This low decoding complexity and the fine granularity make it feasible to efficiently implement the proposed capacityapproaching PC-ldpc convolutional code and the associated trellis-based QC-MAP decoder in next generation ultra-high data rate mobile systems.

关键词： ldpc convolutional code spatially-coupled ldpc decoder complexity IEEE802.11ad MAP decoder

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Implementation of Decoders for ldpc Block codes and ldpc convolutional codes Based on GPUs

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2014年第3期25卷 663-672页

作者： Zhao, Yue Lau, Francis C. M. Hong Kong Polytech Univ Dept Elect & Informat Engn Kowloon Hong Kong Peoples R China

In this paper, efficient ldpc block-code decoders/simulators which run on graphics processing units (GPUs) are proposed. We also implement the decoder for the ldpc convolutional code (ldpcCC). The ldpcCC is derived from a predesigned quasi-cyclic ldpc block code with good error performance. Compared to the decoder based on the randomly constructed ldpcCC code, the complexity of the proposed ldpcCC decoder is reduced due to the periodicity of the derived ldpcCC and the properties of the quasi-cyclic structure. In our proposed decoder architecture, Gamma (Gamma is a multiple of a warp) codewords are decoded together, and hence, the messages of Gamma codewords are also processed together. Since all the Gamma codewords share the same Tanner graph, messages of the Gamma distinct codewords corresponding to the same edge can be grouped into one package and stored linearly. By optimizing the data structures of the messages used in the decoding process, both the read and write processes can be performed in a highly parallel manner by the GPUs. In addition, a thread hierarchy minimizing the divergence of the threads is deployed, and it can maximize the efficiency of the parallel execution. With the use of a large number of cores in the GPU to perform the simple computations simultaneously, our GPU-based ldpc decoder can obtain hundreds of times speedup compared with a serial CPU-based simulator and over 40 times speedup compared with an eight-thread CPU-based simulator.

关键词： ldpc ldpc convolutional code CUDA graphics processing unit (GPU) OpenMP parallel computing ldpc decoder ldpcCC decoder

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A 2.0 Gb/s Throughput Decoder for QC-ldpc convolutional codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2013年第7期60卷 1857-1869页

作者： Sham, Chiu-Wing Chen, Xu Lau, Francis C. M. Zhao, Yue Tam, Wai M. Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

This paper proposes a decoder architecture for low-density parity-check convolutional code (ldpcCC). Specifically, the ldpcCC is derived from a quasi-cyclic (QC) ldpc block code. By making use of the quasi-cyclic structure, the proposed ldpcCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-ldpcCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10(-13) at a bit-energy-to-noise power-spectral-density ratio(E-b/N-0) of 3.55 dB.

关键词： Decoder architecture FPGA implementation ldpc convolutional code QC-ldpc convolutional code

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High Throughput Pipeline Decoder for ldpc convolutional codes on GPU

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IEEE COMMUNICATIONS LETTERS 2015年第12期19卷 2066-2069页

作者： Hou, Yi Liu, Rongke Peng, Hao Zhao, Ling Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China

In this letter, we present a graphics processing unit (GPU)-based ldpc convolutional code (ldpc-CC) pipeline decoder with optimized parallelism. The proposed decoder exploits different granularities of decoding parallelism for both the compute unified device architecture (CUDA) kernel execution stage and the data transfer stage. Moreover, the parameter selection criteria for decoder implementation are designed to avoid exhaustive search of all the combinations of parameters. The experiments are carried out on NvidiaGTX460 and GTX580 platforms. The results demonstrate the proposed decoder achieves about 3 times speedup compared to the existing GPU-based work.

关键词： ldpc convolutional code GPU pipeline decoder parallelism

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Parallel Decoding of ldpc convolutional codes Using OpenMP and GPU

Parallel Decoding of LDPC Convolutional Codes Using OpenMP a...

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17th IEEE Symposium on Computers and Communications (lSCC)

作者： Chan, Chi H. Lau, Francis C. M. Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781467327138

Recently, there have been different applications, namely 10GBase-T Ethernet, video broadcasting and satellite communication, utilizing low-density parity-check (ldpc) codes as the forward-error-correction codes. The main reason is that the error performance of ldpc codes can be very close to the Shannon limit. ldpc codes can be further categorized into ldpc block codes (ldpc-BCs) and ldpc convolutional codes (ldpc-CCs). It has also been discovered that ldpc-CCs usually outperform ldpc-BCs. Simulation of ldpc-BCs and ldpc-CCs can take a lot of time because the decoding algorithms are relatively complex. Fortunately, the decoding steps can be performed in parallel. In this paper, we create three different platforms for simulating the error performance of ldpc-CCs. The first two platforms are run on a Central Processing Unit (CPU) while the third one involves the use of a Graphics Processing Unit (GPU). We show that using GPU can improve the simulation speed substantially.

关键词： CPU error performance GPU ldpc code ldpc convolutional code

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Double-Hamming Based QC ldpc codes with Large Minimum Distance

Double-Hamming Based QC LDPC Codes with Large Minimum Distan...

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IEEE International Symposium on Information Theory (ISIT)

作者： Bocharova, Irina E. Hug, Florian Johannesson, Rolf Kudryashov, Boris D. St Petersburg Univ Informat Technol Mech & Opt Dept Informat Syst St Petersburg 197101 Russia Lund Univ Dept Elect & Informat Technol SE-2210 Lund Sweden

ISBN: (纸本)9781457705953

A new method using Hamming codes to construct base matrices of (J, K)-regular ldpc convolutional codes with large free distance is presented. By proper labeling the corresponding base matrices and tailbiting these parent convolutional codes to given lengths, a large set of quasi-cyclic (QC) (J, K) regular ldpc block codes with large minimum distance is obtained. The corresponding Tanner graphs have girth up to 14. This new construction is compared with two previously known constructions of QC (J, K) -regular ldpc block codes with large minimum distance exceeding (J + 1) !. Applying all three constructions, new QC (J, K) -regular block ldpc codes with J = 3 or 4, shorter codeword lengths and/or better distance properties than those of previously known codes are presented.

关键词： Block codes convolutional codes Hamming codes ldpc convolutional code Labeling Parity check codes Polynomials QC ldpc codes Tanner graph Upper bound base matrices convolutional codes cyclic codes double-Hamming codes graph theory large minimum distance matrix algebra parity check codes quasicyclic codes regular ldpc block codes

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Simulation of ldpc convolutional Decoders with CPU and GPU

Simulation of LDPC Convolutional Decoders with CPU and GPU

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International Conference on Consumer Electronics, Communications and Networks

作者： Chi H. Chan Francis C. M. Lau Department of Electronic and Information Engineering The Hong Kong Polytechnic University

ISBN: (纸本)9781457714146

In this paper, the Sum Product Algorithm (SPA) and the Min-Sum Algorithm (MSA) are used for decoding low-density parity-check convolutional codes (ldpc-CCs). The two algorithms have been implemented and run on three different computing environments. The first environment is a single-threading Central Processing Unit (CPU);the second one is the multi-threading CPU based on OpenMP (Open Multi-Processing);and the third one is the multi-threading Graphics Processing Unit (GPU). The error performance of the ldpc-CCs and the simulation time taken under the three specific computing environments and the two decoding algorithms are evaluated and compared. It is found that the different computing environments produce very similar error results. It is also concluded that using the GPU computing platform can reduce the simulation time substantially.

关键词： CPU Error-correction code GPU ldpc convolutional code OpenMP

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