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An ldpc decoder architecture for Wireless Sensor Network Applications

SENSORS 2012年第2期12卷 1529-1543页

作者： Biroli, Andrea Dario Giancarlo Martina, Maurizio Masera, Guido Politecn Torino Dipartimento Elettron & Telecomunicaz I-10129 Turin Italy

The pervasive use of wireless sensors in a growing spectrum of human activities reinforces the need for devices with low energy dissipation. In this work, coded communication between a couple of wireless sensor devices is considered as a method to reduce the dissipated energy per transmitted bit with respect to uncoded communication. Different Low Density Parity Check (ldpc) codes are considered to this purpose and post layout results are shown for a low-area low-energy decoder, which offers percentage energy savings with respect to the uncoded solution in the range of 40%-80%, depending on considered environment, distance and bit error rate.

关键词： ldpc decoder architecture wireless sensor networks power consumption

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A Fully Parallel Nonbinary ldpc decoder With Fine-Grained Dynamic Clock Gating

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2015年第2期50卷 464-475页

作者： Park, Youn Sung Tao, Yaoyu Zhang, Zhengya Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

Nonbinary ldpc (NB-ldpc) codes, defined over Galois field, offer better coding gain and a lower error floor than binary ldpc codes. However, the complex decoding and large memory requirement have prevented any practical chip implementations. We present a 1.22 Gb/s fully parallel decoder of a GF(64) (160, 80) regular-(2, 4) NB-ldpc code in 65 nm CMOS. The reduced number of edges in NB-ldpc code's factor graph permits a low wiring overhead in the fully parallel architecture. The throughput is further improved by a one-step look-ahead check node design that increases the clock frequency to 700 MHz, and the interleaving of variable node and check node operations that shortens one decoding iteration to 47 clock cycles. We allow each processing node to detect its own convergence and apply dynamic clock gating to save power. When all processing nodes have been clock gated, the decoder terminates and continues with the next input to increase the throughput to 1.22 Gb/s. The dynamic clock gating and decoder termination improve the energy efficiency to 3.03 nJ/b, or 259 pJ/b/iteration, at 1.0 V and 700 MHz. Voltage scaling to 675 mV improves the energy efficiency to 89 pJ/b/iteration for a throughput of 698 Mb/s at 400 MHz.

关键词： Dynamic clock gating ldpc code ldpc decoder architecture nonbinary ldpc code

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Low-Power High-Throughput ldpc decoder Using Non-Refresh Embedded DRAM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2014年第3期49卷 783-794页

作者： Park, Youn Sung Blaauw, David Sylvester, Dennis Zhang, Zhengya Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

The majority of the power consumption of a high-throughput ldpc decoder is spent on memory. Unlike in a general-purpose processor, the memory access in an ldpc decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and further improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline coupling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel ldpc decoder suitable for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm(2) 65 nm ldpc decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the ldpc decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b.

关键词： Embedded DRAM ldpc code ldpc decoder architecture low-power DSP design

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