Games have been one of the most popular applications on smartphones. In order to meet the increasing computational complexity of mobile games, smartphones are now equipped with heterogeneous CPU multi-core architectur...
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Games have been one of the most popular applications on smartphones. In order to meet the increasing computational complexity of mobile games, smartphones are now equipped with heterogeneous CPU multi-core architectures like *** as well as high-performance GPUs. However, the integrated CPUs and GPUs drain the battery quickly, which has become a bottleneck for improving user experience. In addition to traditional Dynamic Voltage and Frequency Scaling (DVFS) technique for CPUs and GPUs power reduction, heterogeneous multi-core processors, such as the *** architecture, have been designed to offer more opportunity for performance-energy tradeoffs. But current processor governors in smartphones can not exploit these power-saving mechanisms wisely, causing considerable energy waste. In this article, we propose a CPU-GPU governing framework that recognizes the performance demand for different game scenes, and select the most energy-efficient hardware configuration for the corresponding scenes. We implement our framework on an ODROID-XU4 mobile platform, and the experiments show that our framework can achieve 26.7, 16.6, and 10.5 percent power saving on average without compromising user experience when compared to the default governor used in our platform and two governors proposed by other researchers, respectively.
Cache prefetching is a traditional way to reduce memory access latency. In multi-core systems, aggressive prefetching may harm the system. In the past, prefetching throttling strategies usually set thresholds through ...
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Cache prefetching is a traditional way to reduce memory access latency. In multi-core systems, aggressive prefetching may harm the system. In the past, prefetching throttling strategies usually set thresholds through certain factors. When the threshold is exceeded, prefetch throttling strategies will control the aggressive prefetcher. However, these strategies usually work well in homogeneous multi-core systems and do not work well in heterogeneous multi-core systems. This paper considers the performance difference between cores under the asymmetric multi-core architecture. Through the improved hill-climbing method, the aggressiveness of prefetching for different cores is controlled, and the IPC of the core is improved. Through experiments, it is found that compared with the previous strategy, the average performance of big core is improved by more than 3%, and the average performance of little cores is improved by more than 24%.
Heterogeneous multi-core processors (HMP) with the same instruction set architecture (ISA) integrate complex high performance big cores with power efficient small cores on the same chip. In comparison with homogeneous...
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Heterogeneous multi-core processors (HMP) with the same instruction set architecture (ISA) integrate complex high performance big cores with power efficient small cores on the same chip. In comparison with homogeneous architectures, HMPs have been shown to significantly increase energy efficiency. However, current techniques to exploit the energy efficiency of HMPs do not consider fair usage of resources that leads to reduced performance predictability, a longer makespan, starvation, and QoS degradation. The effect of different cluster voltage and frequency levels on fairness is another issue neglected by previous task scheduling algorithms. The present study investigates both the fairness problem and energy efficiency in HMPs. This article proposes a heterogeneous fairness-aware energy efficient framework (HFEE) that employs DVFS to meet fairness constraints and provide energy efficient scheduling. The proposed framework is implemented and evaluated on a real heterogeneous multi-core processor. The experimental results indicate that the introduced technique can significantly improve energy efficiency and fairness when compared to Linux standard scheduler and two energy efficient and fairness-aware schedulers.
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