An efficient Fast logarithmic successive cancellation stack (log-scs) polar decoding algorithm is proposed along with its software implementation using single instruction multiple data (SIMD) style processing. Quantit...
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An efficient Fast logarithmic successive cancellation stack (log-scs) polar decoding algorithm is proposed along with its software implementation using single instruction multiple data (SIMD) style processing. Quantitatively, we reduce the decoding complexity by 50% on average, while simultaneously attaining a decoding latency that is only 21% of that of the state-of-the-art Fast successive cancellation list (SCL) polar decoder's software implementation. This is achieved without any loss of error correction performance by applying simplified path-metric (PM) computations for the rate-0, rate-1 and repetition sub-graphs of the proposed Fast log-scs decoder. Furthermore, a software implementation of the 32-bit fixed-point Fast log-scs polar decoder is conceived for x86 processors, which maintains the same block error ratio (BLER) as the floating-point log-scs polar decoder. Additionally, our software implementation is accelerated using SIMD instructions by relying on 512-bit Advanced Vector Extensions (AVX-512) and recursive template meta-programming for the first time, achieving a parallelism of 16, which makes it eminently suitable for the low-latency requirements of software-defined radio systems.
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