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Implementing the Residue logarithmic number system Using Interpolation and Cotransformation

IEEE TRANSACTIONS ON COMPUTERS 2020年第12期69卷 1719-1732页

作者： Arnold, Mark G. Paliouras, Vassilis Kouretas, Ioannis Arnoldware Applicat LLC Laramie WY 82073 USA Univ Patras Elect & Comp Engn Dept Patras 26504 Achaia Greece Univ Patras Elect & Comp Technol Dept Patras 26504 Achaia Greece

The Residue logarithmic number system (RLNS) offers fast multiplication and division, but poses challenges for implementing addition and subtraction because the underlying integer Residue number system (RNS) has slow sign detection. The conventional Binary logarithmic number systems (BLNS) has benefited from interpolation and cotransformation. We propose a dual-path ALU that speculates about the sign detection to adapt interpolation and cotransformation to the limitations of RLNS. Synthesis shows for the same precision and technology, the area of the proposed RLNS circuit is similar to BLNS and much smaller than prior RLNS methods. We also compare against Floating Point (FP).

关键词： Interpolation Hardware Delays Wires Blogs Read only memory Indexes Residue number system logarithmic number system cotransformation interpolation

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logarithmic number system Addition-Subtraction using Fractional Normalization 50

Logarithmic Number System Addition-Subtraction using Fractio...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Tsiaras, Giorgos Paliouras, Vassilis Univ Patras Dept Elect & Comp Engn Patras Greece

ISBN: (纸本)9781467368537

This paper presents a technique for addition/subtraction in the logarithmic number system (LNS) which is based on Floating Point addition/subtraction, specifically on fractional normalization (FN). The proposed technique is analyzed and compared with two other methods for addition/subtraction using 11- and 17-bit word lengths. The results are demonstrated by evaluating complexity and performance of synthesized modules of the above addition/subtraction methods. Modules are synthesized using a 65-nm 0.9V UMC CMOS library.

关键词： logarithmic number system computer arithmetic Mitchell logarithm addition subtraction fractional normalization

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Arithmetic Addition and Subtraction Function of logarithmic number system in Positive Region: An Investigation

Arithmetic Addition and Subtraction Function of Logarithmic ...

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IEEE Student Conference on Research and Development (SCOReD)

作者： Naziri, Siti Zarina Md Ismail, Rizalafande Che Shakaff, Ali Yeon Md Univ Malaysia Perlis Sch Microelect Engn Arau Perlis Malaysia Univ Malaysia Perlis Sch Mechatron Engn Arau Perlis Malaysia

ISBN: (纸本)9781467395724

logarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function in LNS arithmetic as these functions entail complex procedures and circuitry. As its huge potential to be a substitution of FP, there is an urgent need for LNS to improve the performance of both operations. Hence, various studies had been conducted in this area, however most of the research concern the implementation of these operations in the negative region. Therefore, this study is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region and highlights the potential areas for design modifications and improvements. Then, these enhancements will be combined with other arithmetic functions in creating an optimum LNS design to be utilized in any digital image processing system.

关键词： logarithmic number system arithmetic addition subtraction digital image processing

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High speed multiplier using high accuracy floating point logarithmic number system

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SCIENTIA IRANICA 2014年第3期21卷 826-841页

作者： Saha, P. Banerjee, A. Dandapat, A. Bhattacharyya, P. Natl Inst Technol Dept Elect & Commun Engn Shillong 793003 Meghalaya India JIS Coll Engn Dept Elect & Commun Engn Kalyani 741235 W Bengal India Bengal Engn & Sci Univ Dept Elect & Telecommun Engn Sibpur 711103 Howrah India

ASIC implementation of a high speed multiplier using a high accuracy floating point logarithmic number system is reported in this paper. The most popularly used techniques for computing logarithmic calculations for digital signal processors are: Lookup table based implementation, polynomial approximation, and Taylor series expansion. But, all these techniques suffer from low accuracy, due to the choice of having only lower order terms of the expanded series. In the present work, logarithmic conversion is implemented by a floating point (IEEE-754 single precision) converting methodology, thereby eliminating series expansion, which eventually results in high accuracy. The improvement in speed, by avoidance of carry propagation, was achieved through Canonical Signed Digit Code (CSDC) implementation, while the high accuracy was achieved through an error minimization circuitry especially designed for this purpose. The functionality of these circuits was checked, and performance parameters, like propagation delay and dynamic power consumption, were calculated by spice spectre using 90 nm CMOS technology. The propagation delay and power consumption of the resulting (128 x 128) bit multiplier (divider) was only similar to 93 ns and similar to 80 mW, respectively, for a layout area of similar to 25mm(2). This implementation offered a significant improvement in terms of accuracy, delay and power from those reported earlier. (C) 2014 Sharif University of Technology. All rights reserved.

关键词： Canonical sign digit code logarithmic number system Multiplier High speed High accuracy

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Low-precision logarithmic number systems: Beyond Base-2

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2021年第4期18卷 1–25页

作者： Alam, Syed Asad Garland, James Gregg, David Trinity Coll Dublin Lero Dublin 2 Dublin Ireland

logarithmic number systems (LNS) are used to represent real numbers in many applications using a constant base raised to a fixed-point exponent making its distribution exponential. This greatly simplifies hardware multiply, divide, and square root. LNS with base-2 is most common, but in this article, we show that for low-precision LNS the choice of base has a significant impact. We make four main contributions. First, LNS is not closed under addition and subtraction, so the result is approximate. We show that choosing a suitable base can manipulate the distribution to reduce the average error. Second, we show that low-precision LNS addition and subtraction can be implemented efficiently in logic rather than commonly used ROM lookup tables, the complexity of which can be reduced by an appropriate choice of base. A similar effect is shown where the result of arithmetic has greater precision than the input. Third, where input data from external sources is not expected to be in LNS, we can reduce the conversion error by selecting a LNS base to match the expected distribution of the input. Thus, there is no one base that gives the global optimum, and base selection is a trade-off between different factors. Fourth, we show that circuits realized in LNS require lower area and power consumption for short word lengths.

关键词： logarithmic number system quantization error digital arithmetic

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LUT-DSP usage trade-off for re-configurable convolution acceleration core based on small logarithmic floating point representation

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2024年第4期52卷 1864-1871页

作者： Xiong, Botao Fan, Sheng He, Xintong Zhou, Zezhao Yang, Runhua Li, Sicun Shen, Rensheng Chang, Yuchun Dalian Univ Technol Sch Microelect Dalian Peoples R China Dalian Univ Technol Sch Microelect Dalian 116024 Liaoning Peoples R China

The challenge in designing the high-performance field-programmable gate array (FPGA)-based convolution accelerator is to take full advantage of the on-chip computing resources. The reported CNN accelerators always exhaust the on-chip DSPs and leave other computing resources under-utilized. Hence, this brief presents a novel convolution acceleration core based on the small logarithmic floating-point (SLFP) format, which results in three contributions. (1) The SLFP < 3,5 > multiplier is only implemented with 13x LUT6s and operates at 650 MHz with the aid of the carry chain, which provides sufficient accuracy for most CNNs. In addition, a similar structure can be used to imple-ment a SLFP < 3,5 > divider. (2) The DSPs in the TWO24 SIMD mode are cas-caded to implement a 9-input adder tree. The sum of the multiples of 9x elements (e.g., 18x, 27x) is easily obtained by configuring the last DSP in the 9-input adder tree in the accumulation mode, which can support more kernels (e.g., 5 x 5, 128 x 1 x 1) with a high utilization rate (approximate to 90%). (3) The convolu-tion core based on the SLFP format only uses 654x LUT6s and 7x DSPs to achieve 1300 MOPS, 433 MOPS, and 81 MOPS for 3 x 3, 5 x 5, and 128 x 1 x 1 kernel, respectively. In summary, the proposed convolution accelerator not only balances the resource usage of LUT6s and DSPs but also quantizes most CNN models using several simple scaling operations instead of a computing -intensive retraining algorithm because the distribution of SLFP numbers is very similar to FP32 numbers.

关键词： convolutional neural network FPGA architecture logarithmic number system reconfigurable adder tree small floating-point representation

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Low-Power logarithmic number system Addition/Subtraction and Their Impact on Digital Filters

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IEEE TRANSACTIONS ON COMPUTERS 2013年第11期62卷 2196-2209页

作者： Kouretas, Ioannis Basetas, Charalambos Paliouras, Vassilis Univ Patras Dept Elect & Comp Engn GR-26500 Patras Greece

This paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point two's-complement equivalents.

关键词： logarithmic number system computer arithmetic digital filter FIR

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Beating Posits at Their Own Game: Takum Arithmetic 5th

Beating Posits at Their Own Game: Takum Arithmetic

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5th International Conference for Next Generation Arithmetic

作者： Hunhold, Laslo Univ Cologne Parallel & Distributed Syst Grp Cologne Germany

ISBN: (纸本)9783031727085;9783031727092

Recent evaluations have highlighted the tapered posit number format as a promising alternative to the uniform precision IEEE 754 floating-point numbers, which suffer from various deficiencies. Although the posit encoding scheme offers superior coding efficiency at values close to unity, its efficiency markedly diminishes with deviation from unity. This reduction in efficiency leads to suboptimal encodings and a consequent diminution in dynamic range, thereby rendering posits suboptimal for general-purpose computer arithmetic. This paper introduces and formally proves 'takum' as a novel general-purpose logarithmic tapered-precision number format, synthesising the advantages of posits in low-bit applications with high encoding efficiency for numbers distant from unity. Takums exhibit an asymptotically constant dynamic range in terms of bit string length, which is delineated in the paper to be suitable for a general-purpose number format. It is demonstrated that takums either match or surpass existing alternatives. Moreover, takums address several issues previously identified in posits while unveiling novel and beneficial arithmetic properties.

关键词： takum arithmetic tapered number format logarithmic number system dynamic range posit arithmetic

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Novel VLSI Architecture for Fractional-Order Correntropy Adaptive Filtering Algorithm

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2022年第7期30卷 893-904页

作者： Alex, Daney Gogineni, Vinay Chakravarthi Mula, Subrahmanyam Werner, Stefan IIT Palakkad Dept Elect Engn Kozhippara 678557 India Norwegian Univ Sci & Technol NTNU Dept Elect Syst N-7491 Trondheim Norway

Conventional adaptive filters, which assume Gaussian distribution for signal and noise, exhibit significant performance degradation when operating in non-Gaussian environments. Recently proposed fractional-order adaptive filters (FoAFs) address this concern by assuming that the signal and noise are symmetric alpha-stable random processes. However, the literature does not include any VLSI architectures for these algorithms. Toward that end, this article develops hardware-efficient architecture for fractional-order correntropy adaptive filter (FoCAF). We first reformulate the FoCAF for its efficient real-time VLSI implementation and then demonstrate that these reformulations cause negligible performance degradation under the 16-bit fixed-point implementation. Using this reformulated algorithm, we design an FoCAF architecture. Furthermore, we analyze the critical path of the design to select the appropriate level of pipelining based on the sampling rate of the application. According to the critical-path analysis, the FoCAF design is pipelined using retiming techniques to obtain delayed FoCAF (DFoCAF), which is then synthesized using 45-nm CMOS technology. Synthesis results reveal that DFoCAF architecture requires a minimal increase in hardware over the prominent least mean square (LMS) filter architecture and achieves a significant increase in the performance in symmetric alpha-stable environments where LMS fails to converge.

关键词： Very large scale integration Mathematical models Random processes Optimized production technology Computer architecture Real-time systems Hardware -Stable signals adaptive filters fractional-order correntropy criterion logarithmic number system VLSI architectures

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Small logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

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IEEE TRANSACTIONS ON CIRCUITS AND systemS II-EXPRESS BRIEFS 2022年第12期69卷 5119-5123页

作者： Xiong, Botao Fan, Sheng He, Xintong Xu, Tu Chang, Yuchun Dalian Univ Technol Sch Microelect Dalian 116000 Peoples R China

The small floating-point (SFP) multiplier proposed by Xilinx is utilized to implement the convolution neural networks (CNNs). This scheme can balance the resource usage of look-up tables (LUTs) and digital signal processing blocks (DSPs) so that high compute density is achieved on Field Programmable Gate Arrays (FPGAs). In addition, this scheme can quantize the CNNs with several simple scaling operations rather than a lengthy compute intensive retraining process. However, the mantissa field of SFP multiplier is required to be less than or equal to 3-bit, thus significantly restricts the application of this scheme. To figure out this issue, we implement the SFP multiplier in the logarithmic domain such that the multiplication is performed by the addition with the aid of logarithmic and antilogarithmic converters that is referred to as small logarithmic floating-point (SLFP) multiplier. Compared to SFP multiplier (3bit mantissa), the proposed SLFP multiplier can support multiple accuracy levels (3 similar to 5-bit mantissa) with a relatively low overhead (0 similar to 3x LUT6s). Moreover, we utilize the look-ahead carry chain to reduce the delay of addition so that the proposed SLFP multiplier can operate at 650MHz. As a result, the latency (1.5ns, 1x clock cycle) and throughput (650MOPS) of proposed SLFP multiplier (3 similar to 5-bit mantissa) are the same as the SFP multiplier (3-bit mantissa). In the end, the implementation of MobileNet proves that the accuracy level of SFP multiplier (3-bit mantissa) is not sufficient, which can be solved by the proposed SLFP multipliers (5-bit mantissa).

关键词： Floating-point multiplier logarithmic number system convolution neural network FPGA architecture

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