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Generalized Hyperbolic CORDIC and Its logarithmic and Exponential computation With Arbitrary Fixed Base (vol 27, pg 2156, 2019)

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2019年第9期27卷 2222-2222页

作者： Luo, Yuanyong Wang, Yuxuan Ha, Yajun Wang, Zhongfeng Chen, Siyuan Pan, Hongbing Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Jiangsu Peoples R China ShanghaiTech Univ Sch Informat Sci & Technol Shanghai 201210 Peoples R China Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

This paper proposes a generalized hyperbolic COordinate Rotation Digital Computer (GH CORDIC) to directly compute logarithms and exponentials with an arbitrary fixed base. In a hardware implementation, it is more efficient than the state of the art which requires both a hyperbolic CORDIC and a constant multiplier. More specifically, we develop the theory of GH CORDIC by adding a new parameter called base to the conventional hyperbolic CORDIC. This new parameter can be used to specify the base with respect to the computation of logarithms and exponentials. As a result, the constant multiplier is no longer needed to convert base [Formula Omitted] (Euler’s number) to other values because the base of GH CORDIC is adjustable. The proposed methodology is first validated using MATLAB with extensive vector matching. Then, example circuits with 16-bit fixed-point data are implemented under the TSMC 40-nm CMOS technology. Hardware experiment shows that at the highest frequency of the state of the art, the proposed methodology saves 27.98% area, 50.69% power consumption, and 6.67% latency when calculating logarithms; it saves 13.09% area, 40.05% power consumption, and 6.67% latency when computing exponentials. Both calculations do not compromise accuracy. Moreover, it can increase 13% maximum frequency and reduce up to 17.65% latency accordingly compared to the state of the art.

关键词： Digital Signal Processing Chips Fixed Point Arithmetic logarithmic computation Exponential computation Arbitrary Fixed Base GH CORDIC Hardware Implementation Constant Multiplier Computing Exponentials Fixed Point Data Power Consumption Generalized Hyperbolic Coordinate Rotation Digital Computer Approximation Methods Hardware Iterative Methods Very Large Scale Integration Digital Computers Power Demand Matlab Architecture Exponential Generalized Hyperbolic C Oordinate Rotation Digital Computer GH CORDIC Hyperbolic CORDIC Logarithm

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LOGNET: ENERGY-EFFICIENT NEURAL NETWORKS USING logarithmic computation

LOGNET: ENERGY-EFFICIENT NEURAL NETWORKS USING LOGARITHMIC C...

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IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Lee, Edward H. Miyashita, Daisuke Chai, Elaina Murmann, Boris Wong, S. Simon Stanford Univ Stanford CA 94305 USA Toshiba Tokyo Japan

ISBN: (纸本)9781509041176

We present the concept of logarithmic computation for neural networks. We explore how logarithmic encoding of non-uniformly distributed weights and activations is preferred over linear encoding at resolutions of 4 bits and less. logarithmic encoding enables networks to 1) achieve higher classification accuracies than fixed-point at low resolutions and 2) eliminate bulky digital multipliers. We demonstrate our ideas in the hardware realization, LogNet, an inference engine using only bitshift-add convolutions and weights distributed across the computing fabric. The opportunities from hardware work in synergy with those from the algorithm domain.

关键词： Neural networks logarithmic computation approximate computing hardware-software co-design

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LogNet: Energy-efficient neural networks using logarithmic computation

LogNet: Energy-efficient neural networks using logarithmic c...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Edward H. Lee Daisuke Miyashita Elaina Chai Boris Murmann S. Simon Wong Stanford University United States of America

ISBN: (纸本)9781509041183

关键词： Neural networks logarithmic computation approximate computing hardware-software co-design

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Learning accelerator of deep neural networks with logarithmic quantization 7

Learning accelerator of deep neural networks with logarithmi...

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7th IIAI International Congress on Advanced Applied Informatics (IIAI-AAI)

作者： Ueki, Takeo Iwai, Keisuke Matsubara, Takashi Kurokawa, Takakazu Natl Def Acad Japan Dept Comp Sci Yokosuka Kanagawa Japan

ISBN: (纸本)9781538674475

In recent years, Deep Neural Network (DNN)s have become widely spread. Several high-throughput hardware implementations for DNNs have been proposed. One of the key points for hardware implementations of DNNs is to reduce their circuit scale because DNNs require a lot of product-sum operations. Previous papers presented some accelerators using logarithmic quantization to reduce circuit scale by replacing multipliers with shifters. However, most of them are implemented only for inference, and we can find no previous paper using logarithmic quantization for learning. In this paper, a learning accelerator using a logarithmic quantization is proposed. The accelerator uses a stochastic approach for logarithmic quantization. It enables DNNs to learn using logarithmic quantization values. Preliminary evaluation confirmed that DNNs using the proposed method can achieve recognition of MNIST with an accuracy of 97.8%. This evaluation result proves that the proposed method can be used for learning DNNs. The accelerator using the proposed method is implemented on a field-programmable gate array (FPGA) (Xilinx Zynq7020) and synthesized with Xilinx Vivado 2017.1. As a result, it is confirmed to have 2.9 times smaller circuit scale compared with the same FPGA accelerator using 32-bit fixed point number.

关键词： neural networks logarithmic computation approximate computing field-programmable gate arrays

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Learning accelerator of deep neural networks with logarithmic quantization

Learning accelerator of deep neural networks with logarithmi...

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International Congress on Advanced Applied Informatics

作者： Takeo Ueki Keisuke Iwai Takashi Matsubara Takakazu Kurokawa Department of Computer Science National Defence Academy of Japan

ISBN: (纸本)9781538674482;9781538674475

关键词： Neural networks logarithmic computation Approximate computing Field-programmable gate arrays

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Analog synthetic biology

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PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2014年第2012期372卷 7-7页

作者： Sarpeshkar, R. MIT Elect Res Lab Cambridge MA 02139 USA

We analyse the pros and cons of analog versus digital computation in living cells. Our analysis is based on fundamental laws of noise in gene and protein expression, which set limits on the energy, time, space, molecular count and part-count resources needed to compute at a given level of precision. We conclude that analog computation is significantly more efficient in its use of resources than deterministic digital computation even at relatively high levels of precision in the cell. Based on this analysis, we conclude that synthetic biology must use analog, collective analog, probabilistic and hybrid analogdigital computational approaches;otherwise, even relatively simple synthetic computations in cells such as addition will exceed energy and molecular-count budgets. We present schematics for efficiently representing analog DNA-protein computation in cells. Analog electronic flow in subthreshold transistors and analog molecular flux in chemical reactions obey Boltzmann exponential laws of thermodynamics and are described by astoundingly similar logarithmic electrochemical potentials. Therefore, cytomorphic circuits can help to map circuit designs between electronic and biochemical domains. We review recent work that uses positive-feedback linearization circuits to architect wide-dynamic-range logarithmic analog computation in Escherichia coli using three transcription factors, nearly two orders of magnitude more efficient in parts than prior digital implementations.

关键词： analog computation synthetic biology cytomorphic logarithmic computation probabilistic computation bioenergetics

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A hardware algorithm for fast logarithmic computation with exponential convergence rate

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2005年第4期28卷 749-752页

作者： Chen, CY Chen, RL Sheu, MH Feng Chia Univ Dept Informat Engn & Comp Sci Taichung 407 Taiwan Natl Yunlin Univ Sci & Technol Dept Elect Engn Yunlin 640 Taiwan

A hardware algorithm is proposed for improving the speed of the linear digit-recurrence logarithmic algorithm. The convergence rate of this logarithmic algorithm is exponential. Furthermore, the size of the lookup tables used in the algorithm is smaller than the size of the lookup tables used in the digit-recurrence algorithms. When the word length of the operand is less than or equal to 64 bits, the operations involved in each stage of the logarithmic computation only include small table lookup operation, digit-multiplication, and simple square operations. We conclude that the hardware implementation of our proposed algorithm is very efficient.

关键词： logarithmic computation digit-recurrence algorithm reciprocal approximation logarithmic number system

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