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METHOD FOR THE DIAGNOSIS OF A SINGLE INTERMITTENT FAULT IN combinatorial logic circuits.

IEE Journal on Computers and Digital Techniques 1979年第5期2卷 187-190页

作者： Lala, P.K. Missen, James I. Department of Physics City University London UK

The paper presents a technique, based on probability theory, which detects a well behaved intermittent fault in combinatorial logic circuits. The procedure employs repeated applications of tests that detect solid faults in the circuit. The time period, during which a test is repeatedly applied, depends on the probability of detection desired and is derived from the Poisson distribution of statistics. The percentage of faults located using repeated tests via software simulation agrees very well with the statistical prediction.

关键词： logic circuits, combinatorial

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APPLICATION OF B-TERNARY logic TO HAZARD IN combinatorial SWITCHING circuits.

Systems, computers, controls

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Systems, computers, controls 1978年第5期9卷 23-29页

作者： Mukaidono. Masao

It is shown that the problem of whether or not a combinational circuit may contain static hazards can be totally solved using B-ternary logic in which the truth values 0, 1 and one-half are used to represent false, true and ambiguous, respectively. That is, a canonical form which indicates the existence of static hazards by means of B-ternary logic can be constructed. Therefore, for any given combinational switching circuit,various kinds of static hazards contained in the circuit can be detected and identified through the canonical form of the B-ternary logic function corresponding to the circuit. Conversely, a canonical form of the B-ternary logic function which involves any given static hazards can be constructed.

关键词： logic circuits, combinatorial

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combinatorial and Sequential logic circuits with PROMS.

Elektronik Munchen

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Elektronik Munchen 1980年第10期29卷 67-70页

作者： Brendle, Martin

Using bipolar PROMs it is possible to design combining and sequential digital circuits that produce several advantages compared to those with discrete gates and flip-flops. This is demonstrated, taking stepping-motor ... 详细信息

关键词： logic circuits, combinatorial

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MULTIPLE STUCK-AT FAULTS DETECTION IN CMOS COMBINATIONAL GATES

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1991年第1-5期32卷 775-782页

作者： BUONANNO, G LOMBARDI, F SCIUTO, D SHEN, YN POLITECN MILAN DEPT ELECTRMILANITALY TEXAS A&M UNIV SYST DEPT COMP SCICOLLEGE STNTX 77843 UNIV BRESCIA DEPT IND AUTOMATBRESCIAITALY

The problem of designing easily testable CMOS combinational circuits is afforded. Two CMOS structured design techniques are presented. The novelty of this approach relies upon the complete fault detection of single and multiple line stuck-at, transistor stuck-open and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect also a large number of bridging faults. The techniques are both based on the addition of two transistors, a P-FET and a N-FET, placed in series between the P and N sections. In the first case (Dynamic Fully CMOS - DFCMOS), they are controlled by a single input;in the other (Testable Fully CMOS-TFCMOS) there is one input for each additional transistor. The test procedure is defined and it is shown that multiple faults detection can be easily achieved.

关键词： logic circuits, combinatorial

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COMPLETE TEST-GENERATION METHOD FOR ALL STUCK-AT FAULTS IN COMBINATIONAL-circuits

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INTERNATIONAL JOURNAL OF ELECTRONICS 1990年第5期68卷 657-666页

作者： GURAN, H HALICI, U Middle East Technical University Electrical and Electronics Engineering Department Balgat Ankara Turkey

In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure.

关键词： logic circuits, combinatorial

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A THEORY FOR THE DERIVATION OF COMBINATIONAL C-MOS CIRCUIT DESIGNS

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THEORETICAL COMPUTER SCIENCE 1991年第1期90卷 235-251页

作者： HOARE, CAR Oxford University Computing Laboratory Programming Research Group 8-11 Keble Road Oxford OX1 3QD UK

This paper shows how propositional logic may be used to reason about synchronous combinational switching circuits implemented in C-mos. It develops a simple formalism and theory for describing and predicting their behaviour. On this it builds a calculus of design which is driven by proof obligations. The design philosophy for software introduced in [1] is thereby extended to a certain kind of hardware design. No prior knowledge of hardware is assumed of the reader;but useful background, motivation, examples and pictures may be found in [2]. Many of the problems described in that paper have been solved in this one.

关键词： logic circuits, combinatorial

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ANALYSIS OF MULTIVALUED COMBINATIONAL logic-NETWORKS WITH UNCERTAINTY

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INTERNATIONAL JOURNAL OF ELECTRONICS 1988年第2期64卷 255-267页

作者： LLORIS, A MIRO, J UNIV PALMA DE MALLORCA FAC CIENCIASDEPT FISPALMA DE MALLORCASPAIN

The paper presents a procedure for the analysis of uncertainty in multivalued combinational logic networks. The external inputs are presumed to be well defined and uncertainty, to be due only to the behaviour of the network. This, method allows us to establish how the uncertainty in the behaviour of some elements of the network affects the behaviour of the whole network. More specifically, given the designation matrix of each element of the network, we obtain the designation matrix for the whole network.

关键词： logic circuits, combinatorial

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NEW logicAL-SUM AND logicAL-PRODUCT circuits USING CMOS TRANSISTORS AND THEIR APPLICATIONS TO 4-VALUED COMBINATIONAL-circuits

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INTERNATIONAL JOURNAL OF ELECTRONICS 1987年第2期63卷 215-227页

作者： WATANABE, T MATSUMOTO, M LI, T Department of Electrical Engineering Toyo University Kawa-goe-Shi 350 Saitama Pref. Japan

In this paper, the new CMOS circuits for logical-sum and logical-product are proposed. In the case of two inputs, each of such proposed circuits can be composed of a pair of PMOS and NMOS transistors with threshold voltages close to zero volts. The model-parameters of such transistors are presented. It is shown that they are also very well suited for the traditional two-valued logic circuits. Various inverter-circuits to be used in the multiple-valued logic circuits, as well as the above proposed circuits, are also presented. The design method for four-valued combinational circuits using these circuits, together with the examples of their applications, are introduced. The simulation results of such combinational circuits using SPICE-2 are shown with satisfactory characteristics.

关键词： logic circuits, combinatorial

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TESTING FOR STUCK-AT-FAULTS IN MULTIPLE OUTPUT MOS COMBINATIONAL-circuits

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INTERNATIONAL JOURNAL OF ELECTRONICS 1989年第2期66卷 173-182页

作者： ISMAEEL, AA Department of Electrical and Computer Engineering College of Engineering and Petroleum University of Kuwait Safat 13060 P.O. Box 5969 Kuwait

Examines metal oxide semiconductors (MOS) combinational circuits using multiple output configurations. Algorithm used to generate test vectors that are capable of detecting single and multiple stuck faults in multiple output MOS combinational circuits; Relationship between fault coverage and output lines; General test strategy based on transistor sets as functions of output lines.

关键词： logic circuits, combinatorial

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IMPLEMENTATION OF FAULT SIMULATION AND TESTING OF COMBINATIONAL-circuits

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INTERNATIONAL JOURNAL OF ELECTRONICS 1989年第5期66卷 665-678页

作者： MITRA, S SAHA, B Department of Computer Science University of Calcutta Calcutta 700 009 92 Acharya P.C. Road India

A software implementation of a logic simulator capable of testing combinational circuits is presented. Exhaustive testing methodologies like syndrome and index vector testing are applied to make the testing procedure simpler. However, a-tests and b-tests have to be generated and applied in the case of index vector untestable circuits. The method is capable of handling both single and multiple faults. Sample runs have also been included.

关键词： logic circuits, combinatorial

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