Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of thes...
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Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of these techniques are presented with illustrations from practical development projects. Some of the key principles behind self-timed operation are reviewed. Design tools to enable complex practical applications to be engineered are considered. For engineers who wish to find out more a selection of key references is provided.
In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is character...
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In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent, the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the flexibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.
The potential of a Si/SiGe heterostructure for I(2)L circuit application is investigated using an analytic model. Owing to heterojunctions on both the emitter and collector sides of the base, the minority carrier inje...
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The potential of a Si/SiGe heterostructure for I(2)L circuit application is investigated using an analytic model. Owing to heterojunctions on both the emitter and collector sides of the base, the minority carrier injection from the base into the emitter and extrinsic emitter is suppressed. Reduced minority injection leads to a reduced storage charge. Consequently, faster switching speeds are expected in SiGe base double heterojunction bipolar transistors than in their Si counterparts. It is shown that a minimum gate delay of 31 ps for a fanout of 1, and 79 ps for a fanout of 4 can be achieved using a base thickness of 500 Angstrom, base doping of 2 x 10(19) cm(-3) and Ge mole fraction of 0.2. With the addition of a diode in parallel to the emitter-base heterojunction of the SiGe HBT, the intrinsic gate delay can be further reduced to 10.6 and 32 ps for fanouts of 1 and 4, respectively.
The very rapid growth in the complexity of testing logic circuits presents a description problem of increasing severity. In this paper two approaches to this problem are discussed and compared. In the first approach p...
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The very rapid growth in the complexity of testing logic circuits presents a description problem of increasing severity. In this paper two approaches to this problem are discussed and compared. In the first approach path-tracing techniques are used to generate the experiment description of logic circuits from their binary decision diagram representation. In the second approach symbolic execution is used to provide a link between the functional description of a logic circuit, written in a procedural language, and its nonprocedural assertion description. A commercial logic circuit is used throughout the paper as a running example.
The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays i...
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The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.
This paper examines methods for the simulation of digital logic circuits using a demand-driven schedule of evaluation. Demand-driven evaluation, in contrast with conventional event-driven and related methods, enables ...
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This paper examines methods for the simulation of digital logic circuits using a demand-driven schedule of evaluation. Demand-driven evaluation, in contrast with conventional event-driven and related methods, enables the exploitation of lazy evaluation to reduce simulation time. This potential is maximised by an effective ordering of demands in the evaluation schedule. Optimal ordering strategies are described, for both sequential and parallel evaluation cases, and a near-optimal heuristic strategy is identified for two processor evaluation. Simulation results are presented which demonstrate the effectiveness of the method and strategies employed.
Gate fan-in restrictions in logic circuits can be met at the design level by controlling the size of the sums and products of the corresponding Boolean expressions. A single-step procedure for meeting gate fan-in rest...
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Gate fan-in restrictions in logic circuits can be met at the design level by controlling the size of the sums and products of the corresponding Boolean expressions. A single-step procedure for meeting gate fan-in restrictions by limiting the size of the Boolean sums and products while retaining gate minimality is described. The steps are chosen to allow both hand and computer execution.
A statistical model is used as the basis of a rapid, simple and precise method of predicting the fabrication yield of multi‐component logic circuits. The method is based on the statistical behaviour of the individual...
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A statistical model is used as the basis of a rapid, simple and precise method of predicting the fabrication yield of multi‐component logic circuits. The method is based on the statistical behaviour of the individual circuit components.
We consider the problem of minimizing the cycle time of a given pipelined circuit. Existing approaches are suboptimal since they do not consider the possibility of simultaneously resynthesizing the combinational logic...
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We consider the problem of minimizing the cycle time of a given pipelined circuit. Existing approaches are suboptimal since they do not consider the possibility of simultaneously resynthesizing the combinational logic and moving the latches using retiming. In [10] the idea of simultaneous retiming and resynthesis was introduced. We use the concepts presented there to optimize a pipelined circuit to meet a given cycle time. An instance of the pipelined cycle optimization problem is specified by the circuit, a set of input arrival times relative to the clock, a set of output required times relative to the clock, and a given cycle time that it must meet. Given the instance of the pipelined performance optimization problem we construct an instance of a combinational speedup problem. This is specified by a combinational logic circuit, a set of arrival times on the inputs, and a set of required times for the outputs which must be met. We then give a constructive proof that the pipelined problem has a solution if and only if the combinational problem has a solution. This result is significant since it shows it is enough to consider only the combinational speedup problem and all known techniques for that (e.g., [12], [13]) can be directly applied to generate a solution for the pipelined problem.
The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can b...
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The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-level model of the circuit. This results in the detection of all multiple faults having detectable consistent faults. The problem of test set invalidation due to arbitrary signal delays is easily taken care of in domino-CMOS circuits, making such an implementation of a function even more attractive than a fully complementary CMOS implementation, from the testability point of view.< >
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