The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level. Models are developed for estimating currents in a ...
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The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level. Models are developed for estimating currents in a macro-cell (macro) in response to input excitations. Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the maximum current occurs. The macro currents are used to estimate the maximum currents in the segments of power (ground) distribution systems. Some of the algorithms provide tradeoff between runtime and quality of solutions. Experimental results are included.< >
This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulner...
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This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated. (C) 2017 Elsevier Ltd. All rights reserved.
Reliability of logic circuits is emerging as an important concern in scaled electronic technologies. Reliability analysis of logic circuits is computationally complex because of the exponential number of inputs, combi...
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Reliability of logic circuits is emerging as an important concern in scaled electronic technologies. Reliability analysis of logic circuits is computationally complex because of the exponential number of inputs, combinations, and correlations in gate failures. This paper presents three accurate and scalable algorithms for reliability analysis of logic circuits. The first algorithm, called observability-based reliability analysis, provides a closed-form expression for reliability and is accurate when single gate failures are dominant in a logic circuit. The second algorithm, called single-pass reliability analysis, computes reliability in a single topological walk through the logic circuit. It computes the exact reliability for circuits without reconvergent fan-out, even in the presence of multiple gate failures. The algorithm can also handle circuits with reconvergent fan-out with high accuracy using correlation coefficients as described in this paper. The third algorithm, called maximum-k gate failure reliability analysis, allows a constraint on the maximum number (k) of gates that can fail simultaneously in a logic circuit. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed algorithms.
We present a unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits. We characterize such circuits in terms of graphs, lo...
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We present a unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits. We characterize such circuits in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. We model the replacement of a gate in a synchronous logic network by a perturbation of the corresponding logic function, and show that the don't care conditions for the gate optimization represent the bound on this perturbation. We present algorithms to compute such don't care conditions in both the combinational and synchronous case. We comment on the implementation of the algorithms and on the experimental results.
A new switched-current CMOS ternary logic family is presented. Circuit descriptions of the basic gates (inverters, NAND, and NOR) are presented and their performance characteristics are evaluated using SPICE simulatio...
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A new switched-current CMOS ternary logic family is presented. Circuit descriptions of the basic gates (inverters, NAND, and NOR) are presented and their performance characteristics are evaluated using SPICE simulations. The results obtained indicate that the proposed circuits have good noise margins of about 15% of the power supply voltage, and that the propagation delay is less than 1 ns in most cases. Scaled gates, using the constant field scaling law, are found to operate efficiently at reduced power supply voltages, down to 1.0 V. A design procedure to implement any ternary logic function using the proposed gates as basic building blocks is also given.
Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we re...
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Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFA's), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described.
This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basi...
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This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at
In this paper a new method for the minimization of logic circuits is introduced and discussed. The concept involves the breaking down of the complex state table into minimization tables and minimization of each indivi...
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In this paper a new method for the minimization of logic circuits is introduced and discussed. The concept involves the breaking down of the complex state table into minimization tables and minimization of each individual table is then carried out. The attractive features of this method are its simplicity and power, even though a largo number of states are involved. The method hoe been practically tested by designing a control unit of an array processor and found satisfactory.
This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixed-mode model. This paper indicates that monolith...
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This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixed-mode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits provide equal leakage and better delay performance compared with planar 2-D structure through optimized 3-D layout. The monolithic 3-D InGaAs/Ge 6T SRAMs can simultaneously improve the cell stability and performance through optimized 3-D layout. We suggest two 3-D SRAM layout designs for high performance and low power applications, respectively. Moreover, with optimized 3-D layout designs, InGaAs/Ge logic circuits exhibit larger delay improvement, and the 6T SRAMs exhibit larger read access time and time-to-write improvement compared with Si counterparts.
ABSTRACTABSTRACTThe paper presents a procedure for the synthesis or multithreshold circuits with up to four thresholds. The circuit has three operational amplifiers as its kernel. Given the weight-threshold vector of ...
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ABSTRACTABSTRACTThe paper presents a procedure for the synthesis or multithreshold circuits with up to four thresholds. The circuit has three operational amplifiers as its kernel. Given the weight-threshold vector of the boolean function which has to be obtained, the values of the different elements of the circuit are easily obtained. Noise immunity has been computed and has an acceptable value. One example of synthesis is included.
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