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A Unified Parallel Framework for LUT Mapping and logic optimization

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第1期44卷 214-226页

作者： Liu, Tianji Sun, Yang Chen, Lei Li, Xing Yuan, Mingxuan Young, Evangeline F. Y. Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Peoples R China Huawei Huawei Noahs Ark Lab Hong Kong Peoples R China

Lookup-table (LUT) mapping has been extensively utilized in logic synthesis, including being an indispensable step in FPGA design, serving as a building block in high-effort synthesis flows, and providing an algorithmic framework for logic optimization. Hence, a fast mapping algorithm is vital to satisfying the demand for synthesizing high-quality, large-scale modern VLSI designs. This article proposes two efficient GPU-parallel algorithms, namely LUT mapping and and-inverter graph (AIG) optimization using a precomputed database, which rely on a common parallel mapping framework that consists of novel fine-grained parallel mapping passes with high degree of parallelism. The mapping pass is enhanced by specifically tailored cut evaluation and memory management methods for GPUs that enable fast mapping of large circuits with limited GPU memory. Parallel timing analysis passes and parallel cut expansion passes are also proposed for constructing a fully GPU-accelerated LUT mapping flow. The core of parallel AIG optimization is a plugin of the mapping framework, which contains a self-adaptive parallel candidate structure evaluation procedure with high time efficiency and low hardware resource usage. Experiments show that on average, GPU LUT mapping and AIG optimization achieve 34.6x and 99.9x speedup with similar result quality, compared with the high-performance LUT mapper and AIG optimization algorithm with a database implemented in ABC, respectively, on large benchmarks. When combining the two algorithms with other GPU logic optimization algorithms, a GPU-based sequence targeting LUT network synthesis achieves 46.7x speedup with 4.7% smaller area and 0.2% smaller delay over ABC.

关键词： Table lookup logic optimization Delays Graphics processing units Databases Memory management GPU logic optimization logic synthesis parallel algorithms technology mapping

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2024 ICCAD CAD Contest Problem A: Reinforcement logic optimization for a General Cost Function 24

2024 ICCAD CAD Contest Problem A: Reinforcement Logic Optimi...

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Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design

作者： Chung-Han Chou Chih-Jen Hsu Chi-An Wu Kuan-Hua Tu Kwangsoo Han Zhou Li Cadence Design Systems Hsinchu Taiwan Cadence Design Systems San Jose USA Cadence Design Systems Austin USA Cadence Design Systems Austin TX USA

ISBN: (纸本)9798400710773

Traditionally, logic synthesis/optimization metric would be majorly determined by PPA (power, performance, area). However, as the technology node shrinks and the design process becomes extremely complicated, iterative optimization flow and local re-synthesis might be invoked to optimize for more variant purposes. It is necessary to have a methodology which is not just a simple cost-function-based algorithm but also can optimize and legalize a design according to a more complex cost *** this contest, we propose a reinforcement logic optimization problem. The cost is decided by a cost function estimator (black-box executable file), and contestants are expected to develop an intelligent methodology to explore the solution space, optimize, and legalize the design.

关键词： logic optimization

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logic optimization: Redundancy addition and removal using implication relations

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1998年第7期E81D卷 724-730页

作者： Ichihara, H Kinoshita, K Osaka Univ Fac Engn Dept Appl Phys Suita Osaka 5650871 Japan

The logic optimization based on redundancy addition and removal is one of methods which can deal with large-scale logic circuits. In this logic optimization a few redundant elements are added to a logic circuit, and then many other redundant elements which are generated by the redundancy addition are identified and removed. In this paper an optimization method based on redundancy addition and removal using implication relations is proposed. The advantage of the proposed method is to identify removable redundant elements with short time, because the proposed method directly identifies redundant elements using implication relations from two illegal signal assignments which are produced by redundancy addition. The experimental results compared this method with another method show that this method is faster than the another method without declining the optimization ability.

关键词： logic optimization implication redundancy identification

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logic optimization technique for molecular cascades

Logic optimization technique for molecular cascades

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Conference on Nanotechnology II

作者： Färm, P Dubrova, E Tenhunen, H Royal Inst Technol S-16428 Kista Sweden

ISBN: (纸本)0819458333

Molecular cascades introduced in(1) provide new ways to exploit the motion of individual molecules in nanometer-scale structures. Computation is performed by purely mechanical means similarly to the toppling of a row of standing domino. A specific feature of molecular cascades is that an inverter cannot be build, because it would require that all molecules in the inverter's output untopple when the input cascade topples. This is not possible because an untoppled state has higher energy than a toppled one. As a solution, we propose to avoid the need for inverters by representing signals by the dual-rail convention. As a basic building block we use a molecular block, which has four inputs x(1),...,x(4) such that x(3) = x(1)', x(4) = x(2)', and two outputs f(1) = x(1) . x(2) and f(2) = x(3) + x(4). If input variables are available in both complemented and non-complemented form, then any Boolean function can be implemented by a composition of such molecular blocks. We present an experimental tool which first uses a rule-based randomized search to optimize a Boolean network and then maps it into a network of interconnected molecular blocks.

关键词： molecular cascades logic optimization technology mapping

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A Combinational logic optimization Method for Large-Scale SFQ Circuits

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2024年第9期34卷 1页

作者： Lin, Qun Yang, Shucheng Weng, Bicong Ren, Jie Shanghai Univ Shanghai 200444 Peoples R China Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol SIMIT Shanghai 200050 Peoples R China Univ Chinese Acad Sci Beijing Beijing 100049 Peoples R China

This work aims to optimize the superconducting single flux quantum (SFQ) combinational logic synthesis process to cope with the scaling up of superconducting SFQ integration. The majority of current research is based on ABC logic synthesis methods, which do not support multioutput logic gates, including mapping dual data flip-flop, resettable D flip-flop with clear, and their variants. Therefore, in the combinational logic optimization stage, we propose a local optimization method to search for specific logic in Boolean expressions by performing the characteristic representation of matrices to achieve technology mapping for multioutput SFQ gates. Moreover, we use multioutput logic gates to replace the redundant logic in the circuit. We illustrate the operation of our approach on ISCAS benchmark circuits. By adopting our proposed methodology, the performance, power consumption, and area performance of SFQ circuits are improved, which also increases the efficiency of our cell library utilization.

关键词： logic gates logic Circuits Libraries Hardware design languages Superconductivity Superconducting logic circuits Boolean gates logic optimization single flux quantum (SFQ) technology mapping

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An Optimal Pin-Count Design With logic optimization for Digital Microfluidic Biochips

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2015年第4期34卷 629-641页

作者： Dinh, Trung Anh Yamashita, Shigeru Ho, Tsung-Yi Ritsumeikan Univ Grad Sch Informat Sci & Engn Kusatsu 5258577 Japan Ritsumeikan Univ Dept Comp Sci Kusatsu 5258577 Japan Natl Chiao Tung Univ Dept Comp Sci Hsinchu 30010 Taiwan

Digital microfluidic biochips have become one of the most promising technologies for biomedical experiments. In modern microfluidic technology, reducing the number of independent control pins that reflects most of the fabrication cost, power consumption, and reliability of a microfluidic system, is a key challenge for every digital microfluidic biochip design. However, all the previous chip designs sacrifice the optimality of the problem, and only limited reduction on the number of control pins is observed. Moreover, most existing designs cannot satisfy high-throughput demand for bioassays, and thus inapplicable in practical contexts. In this paper, we propose the first optimal pin-count design scheme for digital microfluidic biochips. By integrating a very simple combinational logic circuit into the original chip, the proposed scheme can provide high-throughput for bioassays with an information-theoretic minimum number of control pins. Furthermore, to cope with the rapid growth of the chip's scale, we also propose a scalable and efficient heuristics to reduce the number of control pins. A logic optimization technique, which can be used to reduce the complexity of the integrated combinational logic circuit, is also presented in this paper. Experiments demonstrate that the proposed scheme can obtain much fewer number of control pins compared with the previous state-of-the-art works.

关键词： Digital microfluidics logic optimization pin-count reduction

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LOOPLock: logic optimization-Based Cyclic logic Locking

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第10期39卷 2178-2191页

作者： Chiang, Hsiao-Yu Chen, Yung-Chih Ji, De-Xuan Yang, Xiang-Min Lin, Chia-Chun Wang, Chun-Yao Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30013 Taiwan Yuan Ze Univ Dept Comp Sci & Engn Taoyuan 32003 Taiwan

SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method.

关键词： optimization logic gates Security Electronics packaging Delays Integrated circuits Inverters Cyclic logic locking CycSAT hardware security logic optimization SAT Attack

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Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for logic optimization 34

Accuracy and Size Trade-off of a Cartesian Genetic Programmi...

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34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Berndt, Augusto De Abreu, Brunno A. Campos, Isac S. Lima, Bryan Grellert, Mateus Carvalho, Jonata T. Meinhardt, Cristina Univ Fed Santa Catarina UFSC PPGCC Dept Informat & Estat Florianopolis SC Brazil Univ Fed Rio Grande do Sul UFRGS Inst Informat PGMicro Porto Alegre RS Brazil

ISBN: (纸本)9781665421706

logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Traditional approaches for logic synthesis have been in the spotlight so far. However, due to advances in machine learning and their high performance in solving specific problems, such algorithms appear as an attractive option to improve electronic design tools. In our work, we explore Cartesian Genetic Programming for logic optimization of exact or approximate combinational circuits. The proposed CGP flow receives input from the circuit description in the format of AND-Inverter Graphs and its expected behavior as a truth-table. The CGP may improve solutions found by other techniques used for bootstrapping the evolutionary process or initialize the search from random (unbiased) individuals seeking optimal circuits. We propose two different evaluation methods for the CGP: to minimize the number of AIG nodes or optimize the circuit accuracy. We obtain at least 22.6% superior results when considering the ratio between accuracy and size for the benchmarks used, compared with the teams from the IWLS 2020 contest that obtained the best accuracy and size results. It is noteworthy that any logic synthesis approach based on AIGs can easily incorporate the proposed flow. The results obtained show that their usage may achieve improved logic circuits.

关键词： Cartesian Genetic Programming Electronic Design Automation logic optimization Machine Learning

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State assignment and logic optimization for finite state machines

State assignment and logic optimization for finite state mac...

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IFAC Workshop on Programmable Devices and Embedded Systems (PDES)

作者： Czerwinski, Robert Kania, Dariusz Silesian Tech Univ Inst Elect PL-44100 Gliwice Poland

ISBN: (纸本)9783902661418

An FSM synthesis for PAL-based CPLDs is presented in the paper. A new approach consisted of the original method of the state assignment and PAL-oriented multi-level optimization is proposed. The aim of the proposed heuristic method is oriented on the area minimization. Presented state assignment method takes into consideration elements of two-level minimization, while the essence of PAL-oriented multi-level optimization is to search for multi-output implicants that can be shared by several functions. Results of experiments prove the effectiveness of the method for CPLD structures consist of PAL-based logic blocks.

关键词： state assignment logic optimization finite state machine CPLD FSM

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A New logic optimization Algorithm of Multi-valued logic Function Based on Two-valued logic

A New Logic Optimization Algorithm of Multi-valued Logic Fun...

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2nd International Conference on Frontiers of Manufacturing and Design Science (ICFMD 2011)

作者： Qiu, Jianlin Li, Fen Gu, Xiang Chen, Li Chen, Yanyun Nantong Univ Xinglin Coll Nantong 226019 Jiangsu Peoples R China Nantong Univ Sch Comp Sci & Technol Nantong 226019 Jiangsu Peoples R China

ISBN: (纸本)9783037852828

We make an approach to the logic optimization algorithm including converting multi-valued logic into two-valued logic and converting two-valued logic into multi-valued logic. We discuss the algorithm converting two-valued logic into multi-valued logic on the basis of building an assignment graph and present multi-valued logic optimization algorithm. In this paper, we analyze and study the logic optimization algorithms based on mini-terms and design a software system on logic optimization. It overpasses testing of Benchmark and right validate and it shows that the function of the software system on logic optimization is good and the optimization efficiency is high by testing.

关键词： logic optimization Two-valued logic Multi-valued logic Mini-term

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