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2nd International Symposium of Electronics Design Automation (ISEDA)

作者： Lan, Cunqing Wang, Xinyao Jiang, Zijian Pan, Hongyang Zhu, Keren Bi, Zhaori Yan, Changhao Zeng, Xuan Fudan Univ Sch Microelect State Key Lab Integrated Circuits & Syst Shanghai Peoples R China Chinese Univ Hong Kong CSE Dept Hong Kong Peoples R China

ISBN: (纸本)9798350352047;9798350352030

Recently, demand of higher quality of result (QoR) for logic optimization have spurred numerous studies on generating logic transformation sequence for specific objective. Nevertheless, previous works often suffer from heavy reliance on computing resources or are stuck at local optima. In this work, we propose a logic transformation sequence generator based on domain-specific Monte Carlo tree search (MC-TS). Our framework propose to utilizes information obtained from synthesis tools as context to guild the tree search. Additionally, we implement the algorithm with knowledge retention and adaptive parallelization for further acceleration. Experiments on open-source benchmarks of various scale show that our framework outperforms the state-of-the-art work, Alphasyn, with an average 20.11% efficiency improvement while maintaining comparable effectiveness.

关键词： Electronic design automation logic synthesis logic optimization

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Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for logic optimization 34

Accuracy and Size Trade-off of a Cartesian Genetic Programmi...

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34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Berndt, Augusto De Abreu, Brunno A. Campos, Isac S. Lima, Bryan Grellert, Mateus Carvalho, Jonata T. Meinhardt, Cristina Univ Fed Santa Catarina UFSC PPGCC Dept Informat & Estat Florianopolis SC Brazil Univ Fed Rio Grande do Sul UFRGS Inst Informat PGMicro Porto Alegre RS Brazil

ISBN: (纸本)9781665421706

logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Traditional approaches for logic synthesis have been in the spotlight so far. However, due to advances in machine learning and their high performance in solving specific problems, such algorithms appear as an attractive option to improve electronic design tools. In our work, we explore Cartesian Genetic Programming for logic optimization of exact or approximate combinational circuits. The proposed CGP flow receives input from the circuit description in the format of AND-Inverter Graphs and its expected behavior as a truth-table. The CGP may improve solutions found by other techniques used for bootstrapping the evolutionary process or initialize the search from random (unbiased) individuals seeking optimal circuits. We propose two different evaluation methods for the CGP: to minimize the number of AIG nodes or optimize the circuit accuracy. We obtain at least 22.6% superior results when considering the ratio between accuracy and size for the benchmarks used, compared with the teams from the IWLS 2020 contest that obtained the best accuracy and size results. It is noteworthy that any logic synthesis approach based on AIGs can easily incorporate the proposed flow. The results obtained show that their usage may achieve improved logic circuits.

关键词： Cartesian Genetic Programming Electronic Design Automation logic optimization Machine Learning

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logic optimization by output phase assignment in dynamic logic synthesis 96

Logic optimization by output phase assignment in dynamic log...

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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

作者： Ruchir Puri Andrew Bjorksten Thomas E. Rosser IBM Thomas J. Watson Research Center Yorktown Heights NY IBM Corporation 11400 Burnet Road Austin TX

ISBN: (纸本)9780818675973

Domino logic is one of the most popular dynamic circuit configurations for implementing high-performance logic designs. Since domino logic is inherently noninverting, it presents a fundamental constraint of implementing logic functions without any intermediate inversions. Removal of intermediate inverters requires logic duplication for generating both the negative and positive signal phases, which results in significant area overhead. This area overhead can be substantially reduced by selecting an optimal output phase assignment, which results in a minimum logic duplication penalty for obtaining inverter-free logic. In this paper, we present this previously unaddressed problem of output phase assignment for minimum area duplication in dynamic logic synthesis. We give both optimal and heuristic algorithms for minimizing logic duplication.

关键词： logic optimization logic functions domino logic heuristic algorithms logic duplication area overhead optimal algorithms logic design dynamic logic synthesis minimum logic duplication penalty output phase assignment inverters

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A new method for logic optimization of QCA-based circuits using a golden ball algorithm

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OPTIK 2022年 265卷

作者： Xue, RiXin Tang, Peng Fang, Shudong Chizhou Univ Coll Big Data & Artificial Intelligence Chizhou 247000 Anhui Peoples R China Chizhou Univ Coll Mech & Elect Engn Chizhou 247000 Anhui Peoples R China

Quantum-dot Cellular Automata (QCA) is an approach for constructing low-power digital circuits and various high-performance calculations at the nano-scale. This technique has little power dissipation due to its nature. Implementing circuits using QCA is an active research topic because of the necessary qualities, like short switching time, high device density, and comparatively low power. The primary gates in this technology are the inverter and majority gates, which can function as universal logic gates to build any circuit. This study provides an effective approach to synthesize multi-output Boolean functions using QCA circuits. Due to the NP-hard nature of the logic optimization problem, a golden ball algorithm-based method is utilized to decrease delay time and energy usage in the design process. The simulations utilizing MATLAB software are used to test the functionality of the suggested approach. The empirical findings indicate that the suggested technique performs better than prior methods in numerous instances.

关键词： logic optimization QCA Circuits Golden ball algorithm Nano-scale

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State assignment and logic optimization for finite state machines

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IFAC Proceedings Volumes 2009年第1期42卷 39-44页

作者： Robert Czerwinski Dariusz Kania Silesian University of Technology Institute of Electronics 44–100 Gliwice Akademicka 16

An FSM synthesis for PAL-based CPLDs is presented in the paper. A new approach consisted of the original method of the state assignment and PAL-oriented multi-level optimization is proposed. The aim of the proposed heuristic method is oriented on the area minimization. Presented state assignment method takes into consideration elements of two-level minimization, while the essence of PAL-oriented multi-level optimization is to search for multi-output implicants that can be shared by several functions. Results of experiments prove the effectiveness of the method for CPLD structures consist of PAL-based logic blocks.

关键词： state assignment logic optimization finite state machine CPLD FSM

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Research on the Game Theory and logic optimization and the Applications on Construction of China＇s New Energy Subsidy System

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International Journal of Technology Management 2016年第10期 38-40页

作者： Yi Kuang Renmin University of China District Beijing 100872 P.R. China

In this paper, we conduct research on the game theory and the logic optimization and the applications on construction of China’s new energy subsidy system. The management of energy and the general optimization of energy structure play an important role in the development of the national economy and the upgrading of industrial structure. Therefore, it is the inevitable choice to build a well-off society in an all-round way. The energy projects management in tradition adopts way from bottom to top, namely from the floor of project management starts to collect the data, progressive upward transmission to the high-level, after analysis carries on the management and control to the project, this method had guaranteed the project pays according to progress, quality, cost and other requests, in view of the management of single project. This paper integrates the game theory and the logic optimization to construct the revised system that will be meaningful.

关键词： Game Theory logic optimization New Energy Subsidy System China.

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Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization 02

Prioritized prime implicant patterns puzzle for novel logic ...

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IEL Citation

作者： Kuo-Hsing Cheng Shun-Wen Cheng Department of Electrical Engineering Tamkang University TAIWAN

ISBN: (纸本)0769514413

Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: ""does any rule exist that contains all good?"" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling.

关键词： logic CAD circuit optimisation CMOS logic circuits VLSI low-power electronics circuit CAD prioritized prime implicant patterns puzzle logic synthesis logic optimization CMOS logic pass-transistor logic full swing arbitrary logic function power consumption power-delay product VLSI area efficiency low supply voltage robustness transistor downsizing voltage scaling

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Research on Multi-valued Multi-input Multi-output logic Functions optimization Algorithm

Research on Multi-valued Multi-input Multi-output Logic Func...

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2008年国际电子商务、工程及科学领域的分布式计算和应用学术研讨会

作者： Qiu Jianlin Li Feng Chen Jianping Gu Xiang He Peng School of Computer Science and Technology,Nantong University,Nantong,Jiangsu 226019,P.R.China

In this paper,we make an approach to the logic optimization algorithm including two-valued logic optimization algorithm and multi-valued logic optimization algorithm,then present the algorithm to calculate essential prime cube and special relative redundancy cube and construct two-valued logic *** discuss the algorithm converting two-valued logic into multi-valued logic on the basis of building an assignment graph and present multi-valued logic optimization algorithm,we analyze and study logic function mini-covering based on studying the relevant theory of the multi-valued logic optimization which including the identification of judging macrocosm,the identification of essential prime implicants and relative redundancy and absolute redundancy implicants,and so *** design and realize a software system on logic optimization in programming language C. It overpasses testing of Benchmark and fight validate and it shows that the function of the software system on logic optimization is perfect and the optimization efficiency is so high viaw testing.

关键词： logic optimization Algorithm Two-valued logic Multi-valued logic Mini-covering

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optimization of Threshold logic Networks with Node Merging and Wire Replacement

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2019年第6期24卷 1–18页

作者： Chen, Yung-Chih Zheng, Li-Cheng Wong, Fu-Lian Yuan Ze Univ Dept Comp Sci & Engn 135 Yuan Tung Rd Taoyuan Taiwan

In this article, we present an optimization method for threshold logic networks (TLNs) based on observability don't-care-based node merging. To reduce gate count in a TLN, it iteratively merges two gates that are functionally equivalent or whose differences are never observed at the primary outputs. Furthermore, it is able to identify redundant wires and replace wires for removing more gates. Basically, the proposed method is primarily adapted from an ATPG-based node-merging approach which works for conventional Boolean logic networks. To extend the approach for TLNs, we develop a method for computing mandatory assignments of a stuck-at fault test on a threshold gate and a method for conducting logic implication in a TLN. Additionally, to achieve a better optimization quality, we integrate the proposed method with other optimization methods. The experimental results show that the overall optimization method can save an average of approximately 4.7% threshold gates for a set of TLNs which are generated by using the latest TLN synthesis method. The experimental results also demonstrate the efficiency of the optimization method.

关键词： Threshold logic logic optimization node merging wire replacement

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Combining Relaxation With NCL_X for Enhanced optimization of Asynchronous Null Convention logic Circuits

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IEEE ACCESS 2023年 11卷 104688-104699页

作者： Khodosevych, Danylo Bodoh, Alexander C. Sakib, Ashiq A. Smith, Scott C. Florida Polytech Univ Dept Elect & Comp Engn Lakeland FL 33805 USA Texas A&M Univ Dept Elect Engn & Comp Sci Kingsville TX 78363 USA

Quasi-Delay Insensitive (QDI) asynchronous circuits, such as NULL Convention logic (NCL), are being utilized more and more in industry to mitigate timing issues associated with process, voltage, and temperature (PVT) variations, which are making timing closure for synchronous circuits more problematic as transistor feature size continues to shrink. This paper combines aspects of relaxation optimization with utilizing the NCL_X architecture for select portions of the circuit, resulting in an integrated optimization method for NCL circuits that achieves an average speedup of 6.8% to 12.5%, using on average 24.6% fewer to 3.7% more transistors, compared to existing NCL synthesis and optimization methods.

关键词： Design automation logic optimization asynchronous logic quasi-delay insensitive (QDI) NULL convention logic (NCL)

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