检索结果-内蒙古大学图书馆

Extended Sequential logic for Synchronous Circuit optimization and Its Applications

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2009年第4期28卷 469-477页

作者： Meher, Pramod Kumar Inst Infocomm Res Singapore 138632 Singapore

In this paper, we present a new approach for the extension of sequential logic functionality of D Hip-flop in order to perform an additional Boolean function simultaneously along with Its usual bit-storage function. We show that a combinational function of the form (a . b), (a + b), (a + (b) over bar), or ((a) over bar . b) which occurs frequently in a feedforward path with a D flip-flop could be implemented efficiently by a D flip-flop with RESET or SET provision. Similarly, (a circle plus b) or ((a . b) circle plus c) In the feedback loop with a D flip-flop could he implemented by a T flip-flop by suitable modification of the clock. The use of such extended Sequential logic is found to result in a significant reduction in critical path and saving in area complexity over the direct implementation. Moreover, we present a simple approach for the construction of CMOS T flip-flop by modification of clock signal of D flip-flop, which is found to be more efficient than the T flip-flop derived from JK flip-flop. The extended sequential logic is used for the implementation of finite-field multiplication over GF(2(m)) and carry-save addition of real numbers. In both these cases, the use of extended logic is found to offer a substantial saving in area and time complexity over the conventional implementations.

关键词： Carry-save addition combinational logic digital arithmetic finite-field arithmetic logic optimization sequential logic

来源：评论

学校读者我要写书评

暂无评论

optimization of Reversible logic Networks with Gate Sharing 23

Optimization of Reversible Logic Networks with Gate Sharing

引用

28th Asia and South Pacific Design Automation Conference (ASP-DAC)

作者： Chen, Yung-Chih Chao, Feng-Jie Natl Taiwan Univ Sci & Tech Taipei Taiwan

ISBN: (纸本)9781450397834

logic synthesis for quantum computing aims to transform a Boolean logic network into a quantum circuit. A conventional two-stage flow first synthesizes the given Boolean logic network into a reversible logic network composed of reversible logic gates. Then, it maps each reversible logic gate into quantum gates to generate a quantum circuit. The state-of-the-art method for the first stage takes advantage of the lookup-table (LUT) mapping technology for FPGAs to decompose the given Boolean logic network into sub-networks, and then maps the sub-networks into reversible logic networks. Although every sub-network is well synthesized, we observe that the reversible logic networks could be further optimized by sharing the reversible logic gates belonging to different sub-networks. Thus, in this paper, we propose a new optimization method for the reversible logic networks by sharing gates. We translate the problem of extracting shareable gates to the exclusive-sums-of-product term optimization problem. The experimental results show that the proposed method successfully optimizes the reversible logic networks generated by the LUT-based method. It is able to reduce an average of approximately 4% of quantum gate cost without increasing the number of ancilla lines for a set of IWLS 2005 benchmarks.

关键词： logic optimization reversible logic gate sharing exclusive-sums-of-product minimization

来源：评论

学校读者我要写书评

暂无评论

Evolution of NULL Convention logic Based Asynchronous Paradigm: An Overview and Outlook

引用

IEEE ACCESS 2022年 10卷 78650-78666页

作者： Khodosevych, Danylo Sakib, Ashiq A. Florida Polytech Univ Dept Elect & Comp Engn Lakeland FL 33805 USA

The synchronous design paradigm dominates today's semiconductor industry. However, this clocked approach is facing major challenges with today's high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions.

关键词： logic gates optimization Registers Clocks Delays Wires Testing Asynchronous circuits design automation logic optimization null convention logic testing verification

来源：评论

学校读者我要写书评

暂无评论

A study of theoretical issues in the synthesis of delay fault testability circuits

引用

IEEE TRANSACTIONS ON COMPUTERS 1996年第8期45卷 985-991页

作者： Chakravarty, S Department of Computer Science State University of New York Buffalo NY USA

Multilevel logic optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be ''hazard free delay fault testable'' is presented. In contrast to existing results that consider either ''single path propagating hazard free robust tests'' or ''general robust tests'' we consider ''multiple path propagating hazard free robust tests'' in our analysis.

关键词： delay fault testable circuits logic optimization robust tests testability enhancing transformations testability preserving transformations

来源：评论

学校读者我要写书评

暂无评论

Majority logic Circuit Minimization Using Node Addition and Removal

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2022年第3期41卷 642-655页

作者： Ko, Chang-Cheng Lin, Chia-Chun Chen, Yung-Chih Wang, Chun-Yao Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30013 Taiwan Yuan Ze Univ Dept Comp Sci & Engn Taoyuan 32003 Taiwan

Quantum-dot cellular automata (QCA) is considered as a promising emerging technology due to its low power dissipation and high device density. Since the majority function is the main operation in QCA circuits, minimizing the number of majority gates in QCA circuits is crucial to the corresponding QCA circuit minimization. A previous work used the node-merging technique to replace one target node with an existing substitute node in majority circuits for optimization. However, this technique may fail when no substitute nodes exist for a target node. In this article, we propose an enhanced optimization technique for majority circuits by adding a new node into the circuits and removing the target node and its fanin nodes. The experimental results show that this technique improves the results of the node-merging technique on a set of EPFL logic synthesis benchmarks. Additionally, this enhanced technique can work together with other optimization techniques. The circuit size reduction in the integrated approach reaches 1.26 times as compared to the results using the node-merging technique.

关键词： Circuit faults logic gates optimization Quantum dots Wires Inverters logic circuits logic implication logic optimization majority logic node addition and removal (NAR) node-merging observability do not care (ODC)

来源：评论

学校读者我要写书评

暂无评论

RP-SYN: Synthesis of random pattern testable circuits with test point insertion

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1999年第8期18卷 1202-1213页

作者： Touba, NA McCluskey, EJ Stanford Univ Ctr Reliable Comp Stanford CA 94305 USA Stanford Univ Ctr Reliable Comp Dept Elect Engn & Comp Sci Stanford CA 94305 USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

An automated logic synthesis procedure, called RP-SYN, is described for synthesizing random pattern testable circuits. RP-SYN: takes as an input a two-level description of a circuit and a constraint on the minimum fault detection probability (threshold below which faults are considered random-pattern-resistant), and generates a multilevel implementation which satisfies the constraint while minimizing the literal count, RP-SYN identifies random-pattern-resistant faults and eliminates them through testability-driven factoring combined with test point insertion. By moving the task of test point insertion from the back-end into the synthesis process, RP-SYN reduces design time and enables better optimization of the resulting implementation, Results are shown for benchmark circuits which indicate that RP-SPN can generally reduce the random pattern test length by at least an order of magnitude with only a small area overhead.

关键词： built-in self-test (BIST) computer-aided design design for testability fault coverage integrated circuit testing logic optimization logic synthesis logic transformations pseudorandom testing random pattern testability test points

来源：评论

学校读者我要写书评

暂无评论

Novel efficient full adder and full subtractor designs in quantum cellular automata

引用

JOURNAL OF SUPERCOMPUTING 2020年第3期76卷 2191-2205页

作者： Sadeghi, Mostafa Navi, Keivan Dolatshahi, Mehdi Islamic Azad Univ Najafabad Branch Fac Comp Engn Najafabad Iran Shahid Beheshti Univ Fac Comp Sci & Engn GC Tehran Iran Islamic Azad Univ Najafabad Branch Dept Elect Engn Najafabad Iran

In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.

关键词： Full adder full subtractor (FA FS) Quantum-dot cellular automata (QCA) Nano-electronic circuits logic optimization

来源：评论

学校读者我要写书评

暂无评论

Identification of Threshold Functions and Synthesis of Threshold Networks

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2011年第5期30卷 665-677页

作者： Gowda, Tejaswi Vrudhula, Sarma Kulkarni, Niranjan Berezowski, Krzysztof Arizona State Univ Dept Comp Sci & Engn Tempe AZ 85281 USA Wroclaw Univ Technol Inst Comp Engn Control & Robot PL-50317 Wroclaw Poland

This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This method's success depends on the ordering of the variables in the binary decision diagram (BDD). An alternative data structure, and one that is more compact than a BDD, called a max literal factor tree (MLFT) is introduced. An MLFT is a particular type of factoring tree and was found to be more efficient than a BDD for identifying threshold functions. The threshold identification procedure is applied to the MCNC benchmark circuits to synthesize threshold gate networks.

关键词： Binary decision diagrams Boolean algebra Boolean function logic design logic optimization logic synthesis threshold function threshold logic

来源：评论

学校读者我要写书评

暂无评论

EA-based resynthesis: an efficient tool for optimization of digital circuits

引用

GENETIC PROGRAMMING AND EVOLVABLE MACHINES 2020年第3期21卷 287-319页

作者： Kocnova, Jitka Vasicek, Zdenek Brno Univ Technol IT4Innovat Ctr Excellence Fac Informat Technol Brno Czech Republic

Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Unfortunately, we are facing another problem-scalability of representation. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. To overcome this issue, we propose to apply the concept of local resynthesis in this work. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. When applied appropriately, this approach can mitigate the problem of scalability of representation. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. A huge improvement was achieved especially for the arithmetic circuits. On average, the proposed method was able to remove 25.1% more gates.

关键词： Cartesian genetic programming Evolutionary resynthesis logic optimization

来源：评论

学校读者我要写书评

暂无评论

An Efficient Reinforcement Learning Based Framework for Exploring logic Synthesis

引用

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2024年第2期29卷 1-33页

作者： Qian, Yu Zhou, Xuegong Zhou, Hao Wang, Lingli Fudan Univ State Key Lab Integrated Chips & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China

logic synthesis is a crucial step in electronic design automation tools. The rapid developments of reinforcement learning (RL) have enabled the automated exploration of logic synthesis. Existing RL based methods may lead to data inefficiency, and the exploration approaches for FPGA and ASIC technology mapping in recent works lack the flexibility of the learning process. This work proposes ESE, a reinforcement learning based framework to efficiently learn the logic synthesis process. The framework supports the modeling of logic optimization and technology mapping for FPGA and ASIC. The optimization for the execution time of the synthesis script is also considered. For the modeling of FPGA mapping, the logic optimization and technology mapping are combined to be learned in a flexible way. For the modeling of ASIC mapping, the standard cell based optimization and LUT optimization operations are incorporated into the ASIC synthesis flow. To improve the utilization of samples, the Proximal Policy optimization model is adopted. Furthermore, the framework is enhanced by supporting MIG based synthesis exploration. Experiments show that for FPGA technology mapping on the VTR benchmark, the average LUT-Level-Product and script runtime are improved by more than 18.3% and 12.4% respectively than previous works. For ASIC mapping on the EPFL benchmark, the average Area-Delay-Product is improved by 14.5%.

关键词： Reinforcement learning logic optimization technology mapping Andinverter graph Majority-inverter graph

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：