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Reed-Muller function optimization techniques with onset table

Journal of Zhejiang University-Science C(Computers and Electronics) 2011年第4期12卷 288-296页

作者： Lun-yao WANG Yin-shui XIA Xie-xiong CHEN A. E. A. ALMAINI Department of Information Science and Electronic Engineering Zhejiang University Hangzhou 310027 China Faculty of Information Science and Engineering Ningbo University Ningbo 315211 China School of Engineering Napier University Edinburgh EH10 5DT UK

By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table,an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting the common variables using the onset ***,by employing the multiplexer model,the algorithm is extended to optimize multi-level multi-output mixed-polarity RM *** proposed algorithm is implemented in C language and tested using some MCNC *** results show that the proposed algorithm can obtain a more compact RM form than that under fixed *** with published results,the proposed algorithm makes a significant speed improvement,with a small increase in the number of literals.

关键词： logic optimization Reed-Muller functions Multi-level Mixed polarity Onset table

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Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2000年第2期5卷 193-225页

作者： Cong, J Hwang, YY Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

In this paper we study structural gate decomposition in general, simple gate networks for depth-optimal technology mapping using K-input Lookup-Tables (K-LUTs). We show that (1) structural gate decomposition in any K-bounded network results in an optimal mapping depth smaller than or equal to that of the original network, regardless of the decomposition method used;and (2) the problem of structural gate decomposition for depth-optimal technology mapping is NP-hard for K-unbounded networks when K greater than or equal to 3 and remains NP-hard for K-bounded networks when K greater than or equal to 5. Based on these results, we propose two new structural gate decomposition algorithms, named DOGMA and DOGMA-m, which combine the level-driven node-packing technique (used in Chortle-d) and the network flow-based labeling technique (used in FlowMap) for depth-optimal technology mapping. Experimental results show that (1) among five structural gate decomposition algorithms, DOGMA-m results in the best mapping solutions;and (2) compared with speed_up (an algebraic algorithm) and TOS (a Boolean approach), DOGMA-m completes decomposition of all tested benchmarks in a short time while speed_up and TOS fail in several cases. However, speed_up results in the smallest depth and area in the following technology mapping steps.

关键词： computer-aided design of VLSI decomposition delay minimization FPGA logic optimization programmable logic simplification synthesis system design technology mapping

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Multi-output majority gate-based design optimization by using evolutionary algorithm

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SWARM AND EVOLUTIONARY COMPUTATION 2013年 10卷 25-30页

作者： Tehrani, Mohammad A. Navi, Keivan Kia-kojoori, Ali Shahid Beheshti Univ GC Nanotechnol & Quantum Comp Lab Tehran Iran Univ Calif Irvine Elect & Comp Engn Irvine CA 92714 USA

In this paper, a novel efficient method for optimizing multi-output majority gate based designs is proposed. Majority gate is a fundamental Boolean operator in some nano-scale technologies such as quantum-dot cellular automata (QCA). As a result, the design optimization must be directly implemented on majority gates instead of optimizing the design for AND-OR gates. In some other nanotechnologies, a fundamental element is Minority gate which could be simply converted to majority gate by the De Morgan's theorem. Here, the proposed optimization method works on the basis of evolutionary computation and can reduce both the number of majority gates and the worst-case delay of the circuit. The method is compared to some other optimization algorithms and its efficiency is verified. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Quantum-dot cellular automata Majority gate logic optimization Evolutionary algorithm

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H.264 Deblocking Speedup

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2009年第8期19卷 1178-1182页

作者： Lou, Jian Jagmohan, Ashish He, Dake Lu, Ligang Sun, Ming-Ting Univ Washington Dept Elect Engn Seattle WA 98195 USA IBM Corp Thomas J Watson Res Ctr Dept Multimedia Technol Yorktown Hts NY 10598 USA

This letter tackles the problem of reducing the complexity of H.264 decoding. Since deblocking accounts for a significant percentage of H.264 decoding time, our focus is on the H.264 in-loop deblocking filter. Observing that branch operations are costly and that in the deblocking process there are events with significantly high probability of occurrence, we regroup and simplify the branch operations. We apply the idea of Huffman tree optimization to speed up the boundary strength derivation and the true-edge detection by taking advantage of the biased statistical distribution. Our analyses and experiments show that the proposed techniques can reduce the deblocking computation time typically by a factor of more than seven times, while. maintaining the bit-exact output.

关键词： Deblocking H.264 logic optimization speedup statistics dependent decoding

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Optimizing Carry-Lookahead logic Through A Comparison of PMOS and NMOS Block Inversions

Optimizing Carry-Lookahead Logic Through A Comparison of PMO...

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IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY (EIT)

作者： Binggeli, Mat Denton, Spencer Muppaneni, Naga Spandana Chiu, Steve

ISBN: (纸本)9781479988020

The fast performance of a carry-lookahead adder (CLA) comes from the ability to input a carry signal into each full adder block that depends on all preceding adder blocks. While the translation of this carry signal logic into CMOS transistors has a unique solution, this paper demonstrates that there are four different ways to connect the PMOS and NMOS transistors to V-dd, ground, and the output. Each method is analyzed according to its speed performance to find the most desirable CMOS configuration. This configuration is further improved through transistor sizing to achieve the most optimized CLA carry circuit. The result is given as a schematic, as well as a stick diagram.

关键词： carry-lookahead adder (CLA) logic optimization block inversion transistor sizing delay reduction

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Delay-Driven Physically-Aware logic Synthesis with Informed Search 41

Delay-Driven Physically-Aware Logic Synthesis with Informed ...

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41st IEEE International Conference on Computer Design (ICCD)

作者： Zhu, Linyu Guo, Xinfei Shanghai Jiao Tong Univ Univ Michigan Shanghai Jiao Tong Univ Joint Inst Shanghai Peoples R China

ISBN: (纸本)9798350342918

A typical design flow is separated into front-end and back-end stages, incurring huge number of iteration loops between logic synthesis and place and route to close timing. This has been even worse in advanced technology where wire delay dominates timing. It becomes increasingly important to integrate physical awareness in the logic synthesis optimization processes to achieve better timing correlations. To tackle the physically-aware synthesis challenges, in this paper, we formulate the whole design flow as a multi-stage search problem, where informed search algorithms are utilized to perform efficient search with additional guidance. By incorporating a newly-developed learning-based routing-aware timing prediction model in the inform value function, a delay-driven physically-aware synthesis methodology called DDPAS is proposed, enabling efficient logic optimization with awareness of final routed design. The framework pairs with various search algorithms and learning-based strategies. Evaluation results show that the greedy search based DDPAS improves total negative slack (TNS) by over 58% and achieves over 7% power savings when compared to its counterpart, and the reinforcement learning (RL) based DDPAS delivers 65.6% improvement in terms of TNS and 12.1% power savings compared to a state of the art RL-based logic synthesis framework. Overall, DDPAS yields to better final QoR after routing and significantly reduces the timing closure cycles.

关键词： logic optimization Physically-aware synthesis Timing closure Informed search QoR

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Multiplexer restructuring for FPGA implementation cost reduction

Multiplexer restructuring for FPGA implementation cost reduc...

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42nd Design Automation Conference

作者： Metzgen, P Nancekievill, D Altera European Technol Ctr High Wycombe Bucks England

ISBN: (纸本)1595930582

This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number of Lookup Tables (LUTs) needed to implement multiplexers. The algorithm relies on reimplementing 2:1 multiplexer trees using efficient 4:1 multiplexers. The key to the algorithm's performance lies in exploiting the observation that most multiplexers occur in busses. New optimizations are employed which pay a small cost in logic that is shared across the bus to achieve a reduction in the logic required for every bit of the bus.

关键词： FPGA multiplexers restructuring recoding busses logic optimization synthesis

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Basic Operations And Structure Of An FPGA Accelerator For Parallel Bit Pattern Computation

Basic Operations And Structure Of An FPGA Accelerator For Pa...

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IEEE International Conference on Rebooting Computing (ICRC)

作者： Dietz, Henry Eberhart, Paul Rule, Ashley Univ Kentucky Elect & Comp Engn Lexington KY 40506 USA

ISBN: (纸本)9781665423328

Parallel Bit Pattern computing (PBP) has been proposed as a way to dramatically reduce power consumption per computation by minimizing the total number of gate operations. In part, this reduction is accomplished by employing aggressive compiler optimization technology to gate-level representations of computations at runtime. Massive SIMD parallelism is used to obtain speedups while executing the optimized bit-serial code. However, the PBP model also can potentially exponentially reduce the number of active gates for each such operation by recognizing and operating on symbolically-compressed patterns of bits, rather than on each individual bit within a vector. This not only provides for efficient execution of traditional parallel code, but by using bit vectors to represent entangled superposition, enables quantum-like computation to be efficiently implemented using conventional circuitry. Building on lessons learned from various software and Verilog prototypes, this paper proposes a new set of basic operations and interface structure suitable for using inexpensive Xilinx Zynq-7000 boards to implement FGPA-hardware-accelerated PBP computation. Emphasis is on how these operations will implement quantum-like computation, as the first prototype system is currently still under development.

关键词： Computer Architecture Parallel Bit Pattern Computing SIMD Optimizing Compilers logic optimization

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Resynthesis of logic circuits using machine learning and reconvergent paths 24

Resynthesis of logic circuits using machine learning and rec...

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24th Euromicro Conference on Digital System Design (DSD)

作者： Kocnova, Jitka Vasicek, Zdenek Brno Univ Technol Fac Informat Technol IT4Innovat Ctr Excellence Brno Czech Republic

ISBN: (纸本)9781665427036

Boolean network scoping represents a common approach incorporated in conventional synthesis tools for maintaining good scalability of the synthesis process. Recently, an approach to the local resynthesis based on combination of evolutionary optimization with the principle of Boolean network scoping has been proposed. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. The main advantage of the local resynthesis is that it can mitigate the problem of scalability of representation which is typical to the evolutionary algorithms as the efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing circuit complexity. Unfortunately, the efficiency of local resynthesis depends on the efficiency of the sub-circuit extraction process. We propose an alternative method, based on the reconvergent paths. The evaluation is performed on a set of highly optimized benchmark problems representing various real-world controllers, logic and arithmetic circuits. The method provides better results compared to the state-of-the-art logic synthesis tool and evolutionary optimization techniques operating locally and globally. A substantially higher number of redundant gates was removed in more than 70% cases, while keeping the computational effort at the same level. A huge improvement was achieved especially for the controllers. On average, the proposed method was able to remove more than 14.3% of gates. The highest achieved gate reduction was more than 45% of gates.

关键词： logic optimization Cartesian Genetic Programming Evolutionary Resynthesis

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Abnormal Analysis and optimization of Reactive Power Control Strategy in UHVDC System 2

Abnormal Analysis and Optimization of Reactive Power Control...

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IEEE 2nd International Conference on Power Science and Technology (ICPST)

作者： Li, Qiang Liu, Ziqian Zhang, ShiHong Du, Aiping Hu, Jian China Southern Power Grid Co Ltd EHV Power Transmiss Co Dali Bur Dali Peoples R China Kunming Univ Sci & Technol Fac Elect Engn Kunming Yunnan Peoples R China

ISBN: (纸本)9798350349047;9798350349030

This paper introduces the +/- 800kV Xindong HVDC transmission project AC filter configuration, reactive power control function, and filter switching strategy. Aiming at the problem of reactive power control miscut AC filter in the field debugging, the targeted filter switching strategy optimization measures are proposed, and the correctness and reliability of the optimization measures are verified by RTDS simulation test and field test. It can effectively avoid the power loss or latch-up risk of DC system due to reactive power failure, and has certain reference significance for the design, debugging and fault analysis of subsequent DC transmission projects.

关键词： UHVDC reactive power control miscut filter HVDC blocking logic optimization

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