In this paper, we present implementation of an educational microcomputer named Edulent. Schematic and VHDL design entry versions are compared. Microcomputer is designed to be implemented in any medium complexity progr...
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In this paper, we present implementation of an educational microcomputer named Edulent. Schematic and VHDL design entry versions are compared. Microcomputer is designed to be implemented in any medium complexity programmable logic integrated circuit. It is tested on development board based on Xilinx SpartanIIE family FPGA chip, that is connected to personal computer. Software support running on personal computer is developed and consists of all necessary modules to operate such an educational microcomputer. Some of the hardware and software implementation details are presented
The amount of data collected and stored in databases is growing considerably for almost all areas of human activity. Processing this amount of data is very expensive, both humanly and computationally. This justifies t...
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The amount of data collected and stored in databases is growing considerably for almost all areas of human activity. Processing this amount of data is very expensive, both humanly and computationally. This justifies the increased interest both on the automatic discovery of useful knowledge from databases, and on using parallel processing for this task. Multi relational data mining (MRDM) techniques, such as inductive logic programming (ILP), can learn rides from relational databases consisting of multiple tables. However, ILP systems are designed to run in main memory and can have long running times. We propose a pipelined data-parallel algorithm for ILP. The algorithm was implemented and evaluated on a commodity PC cluster with 8 processors. The results show that our algorithm yields excellent speedups, while preserving the quality of learning
Ladder logic diagram (LLD) as the interfacing programming language of programmable logic controllers (PLCs) is utilized in modern discrete event control systems. However, LLD is hard to debug and maintain in practice....
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Ladder logic diagram (LLD) as the interfacing programming language of programmable logic controllers (PLCs) is utilized in modern discrete event control systems. However, LLD is hard to debug and maintain in practice. This is due to many factors such as non-structured nature of LLD, the LLD programmers' background, and the huge sizes of real world LLD. In this paper, we introduce a recurrent neural network (RNN) based technique for PLC program diagnosis. A manufacturing control system example has been presented to illustrate the applicability of the proposed algorithm. This method could be very advantageous in reducing the complexity in PLC control programs diagnosis because of the ease of use of the RNN compared to debugging the LLD code.
Mozart/Oz is an advanced development platform for intelligent, distributed, powerful and highly functional applications, developed under the European ACCLAIM project. The platform at present lacks a tool for agent com...
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Mozart/Oz is an advanced development platform for intelligent, distributed, powerful and highly functional applications, developed under the European ACCLAIM project. The platform at present lacks a tool for agent communications based on a standard such as ACL-FIPA or KQML. In this work, a tool for agent communication in Mozart/Oz based on KQML has been developed. The communication platform was designed, moreover, as a modular architecture that permits flexibility, high efficiency and inter-operability, which considerably enhances the extensibility of the system. In this paper, this architecture is presented, together with a comparative analysis against two of the most popular agent development platforms in Java, one of which uses KQML (JATLite) and the other, FIPA/ACL (JADE).
In this paper we present a flexible automatic test generation framework to detect a variety of design faults in systems with behavioral VHDL descriptions. Predefined fault models may range from the commonly used state...
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In this paper we present a flexible automatic test generation framework to detect a variety of design faults in systems with behavioral VHDL descriptions. Predefined fault models may range from the commonly used state coverage and transition coverage models to any other fault models which can be described as a set of non-linear constraints on the system's behavior. The test generation problem is formulated as a constraint logic programming problem (CLP) and an industrial CLP engine is used to solve it.
This work describes the implementation of two different BISR algorithms for memories with spare rows and columns. The choice of BISR technology must depend on the final net yield due to area, susceptibility to defects...
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This work describes the implementation of two different BISR algorithms for memories with spare rows and columns. The choice of BISR technology must depend on the final net yield due to area, susceptibility to defects, and repair probability. The Single Deferral algorithm has near the minimal memory requirement. The greedy algorithm is a standard heuristic algorithm that iteratively repairs the line with the most excess defects. The memory requirement for the greedy algorithm is quadratic in the number of spares while Single Deferral is linear. Since the repair probability with Single Deferral is near optimal, it is more cost-effective than greedy.
Checking various temporal requirements is a key dependability concern in safety-critical systems. As model-checking approaches do not scale well to systems of high complexity the runtime verification of temporal requi...
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Checking various temporal requirements is a key dependability concern in safety-critical systems. As model-checking approaches do not scale well to systems of high complexity the runtime verification of temporal requirements has received a growing attention recently. This paper presents a code-generation based method for runtime evaluation of linear temporal logic formulae over program execution traces. The processing-power requirements of our solution are much lower than in case of previous approaches enabling its application even in resource-restricted embedded environments.
This paper proposes a new approach to negation. While most theories for negation are based on the logic paradigm, our theory is constructed based on the equivalent transformation (ET) computation model, since the ET c...
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This paper proposes a new approach to negation. While most theories for negation are based on the logic paradigm, our theory is constructed based on the equivalent transformation (ET) computation model, since the ET computation model provides us with "decomposability of programs." A negative constraint has a domain that is the complement of the semantics of the corresponding declarative description. Computation of negation in the ET paradigm is realized by equivalent transformation of declarative descriptions including negative constraints. For each negative constraint in a definite clause, a new declarative description is produced and transformed equivalently. When it is transformed to a set of unit clauses, the negative constraint is solved. Each unit clause returns a simple constraint to the "caller" clause. This paper proves two theorems that provide a basis for such equivalent transformation of negative constraints.
Boolean equation systems (BESs) allow to represent various problems encountered in the area of propositional logic programming and verification of concurrent systems. Several sequential algorithms for global and local...
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Boolean equation systems (BESs) allow to represent various problems encountered in the area of propositional logic programming and verification of concurrent systems. Several sequential algorithms for global and local BES resolution have been proposed so far, mainly in the field of verification; however, these algorithms do not scale up satisfactorily as the size of BESs increases. In this paper, we propose a distributed algorithm, called DSOLVE, which performs the local resolution of a BES using a set of machines connected by a network. Our experiments for solving large BESs using clusters of PCs show linear speedups and a scalable behaviour of DSOLVE w.r.t. its sequential counterpart.
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