A single poly-silicon trench gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedd...
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A single poly-silicon trench gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedded application. The trenched floating gate (FG) combining with a deep-N-well implanted region guarantees high coupling ratio for CHEI programming and source side FN erasing operation. This cell array in a NOR-type array features fast random access capacity and IIF/sup 2/ cell size.
FELIX is a new design space exploration tool and graphical integrated development environment (IDE) for the programming of coarse-grained reconfigurable architectures. Its main and novel advantage is the use of rewrit...
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FELIX is a new design space exploration tool and graphical integrated development environment (IDE) for the programming of coarse-grained reconfigurable architectures. Its main and novel advantage is the use of rewriting rules and logical strategies for the automated generation of alternative functionally equivalent implementations from a single mathematical specification. The user selection of the rewriting logic strategies to be applied determines the resulting implementations, making it possible to quickly generate, simulate and evaluate alternative implementations that are logically equivalent. The FELIX system includes an interface to the KressArray Xplorer for hardware design-space exploration. The current version of the tool is targeted for the pact extreme processing platform (XPP), with support for additional architectures planned in future versions.
This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for...
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This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known earliest deadline first (EDF) technique to the FPGA execution model. Although the algorithm reveals good scheduling performance, it lacks an efficient schedulability test and requires a high number of FPGA configurations. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method is inferior to the EDF-based technique regarding schedulability, it comes with a fast schedulability test and greatly reduces the number of required FPGA configurations.
A technique has been devised which, via consideration of the program nodes executed during fitness evaluation, allows a genetic programming system to determine many instances in which invocation of the fitness functio...
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A technique has been devised which, via consideration of the program nodes executed during fitness evaluation, allows a genetic programming system to determine many instances in which invocation of the fitness function can be avoided. The nature of Boolean logic problems renders them of particular interest as a focus of study for the application of this technique, and experimental evidence shows that significant speed-ups in execution time can be achieved when evolving solutions to these problems.
While aspect-oriented modeling has been recognized as a useful means of improving the modularity of software design, the de facto standard modeling language UML lacks first-class model elements representing aspects an...
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While aspect-oriented modeling has been recognized as a useful means of improving the modularity of software design, the de facto standard modeling language UML lacks first-class model elements representing aspects and does not provide genuine support for aspect-oriented modeling. We propose a simple extension of UML class diagrams which contains a very generic pointcut and advice language and facilitates to model with aspects. Using this approach, we achieve a better separation of concerns as well as more redundancy reduction in UML class diagrams and make them thus more readable and better maintainable.
Improperly validated user input is the underlying root cause for a wide variety of attacks on Web-based applications. Static approaches for detecting this problem help at the time of development, but require source co...
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Improperly validated user input is the underlying root cause for a wide variety of attacks on Web-based applications. Static approaches for detecting this problem help at the time of development, but require source code and report a number of false positives. Hence, they are of little use for securing fully deployed and rapidly evolving applications. We propose a dynamic solution that tags and tracks user input at runtime and prevents its improper use to maliciously affect the execution of the program. Our implementation can be transparently applied to Java classfiles, and does not require source code. Benchmarks show that the overhead of this runtime enforcement is negligible and can prevent a number of attacks
The performance of an e-commerce application can be measured according to technical metrics but also following business indicators. The revenue obtained by a commercial Web application is directly related to the amoun...
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The performance of an e-commerce application can be measured according to technical metrics but also following business indicators. The revenue obtained by a commercial Web application is directly related to the amount of clients that complete business transactions. In technical terms, a business transaction is completed when a Web client successfully finishes a browsing session. In this paper we introduce a novel Web server architecture that combines the best aspects of both the multithreaded and the event-driven architectures, the two major existing alternatives, to create a server model that offers an improved performance in terms of user session completions without loosing the natural ease of programming characteristic of the multithreading paradigm. We describe the implementation of this architecture on the Tomcat 5.5 server and evaluate its performance. The obtained results demonstrate the feasibility of the hybrid architecture and the performance benefits that this model introduces for e-commerce applications.
An integrated fault tolerant control solution calls for a nonlinear adaptive controller with universal approximation capability and guaranteed stability. To fulfill this requirement, we propose the use of neural netwo...
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An integrated fault tolerant control solution calls for a nonlinear adaptive controller with universal approximation capability and guaranteed stability. To fulfill this requirement, we propose the use of neural networks trained online under a globalized dual heuristic programming architecture supervised by a decision logic capable of identifying controller malfunctions in early stages and providing new avenues with greater probability of convergence using information from a dynamic model bank. The classification and distinction of controller malfunctions and of the faults in the system is achieved through three independent quality indexes. Proof-of- the-concept simulations of nonlinear plants demonstrate the approach legitimacy.
Ensuring that disclosure of information to outside entities is in conformance with the enterprise privacy policies is of utmost concern for all enterprises dealing with consumer information. The existing protection me...
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Ensuring that disclosure of information to outside entities is in conformance with the enterprise privacy policies is of utmost concern for all enterprises dealing with consumer information. The existing protection measures proposed for meeting this goal are inadequate. In this paper we present an approach in which the privacy label taxonomy is developed to classify information types in an enterprise by their privacy labels. Inference analysis is performed on the information types using a disjunctive logic programming technique to detect violations of privacy labeling semantics in various information types. The analysis also provides the technique to deal with such violations so as to achieve a violation-free privacy labeling scheme.
Formal logic has been considered as one of the advanced topics in computing that students do not grasp easily. But the inherent nature of formal logic makes itself a natural choice for forming an overbearing organizin...
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Formal logic has been considered as one of the advanced topics in computing that students do not grasp easily. But the inherent nature of formal logic makes itself a natural choice for forming an overbearing organizing structure, which can be utilized in providing scaffolding during instructional process. This paper discusses the role of formal logic in teaching information science and information systems. We claim that formal logic can be used to realize the modern instruction design principles by ensuring activation of relevant prior knowledge and experiences when learner moves from one topic to another. The paper also describes the successful implementation and evaluation of an on-line teaching tool utilizing predicate logic notation to assist learners in mastering a difficult to learn Unix/Linux system administration command.
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