This paper describes an approach towards workflow management based on the combination of learning and planning. Assuming that processes cannot be fully described at build-time, the approach makes use of learning techn...
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This paper describes an approach towards workflow management based on the combination of learning and planning. Assuming that processes cannot be fully described at build-time, the approach makes use of learning techniques, namely inductive logic programming (ILP), in order to discover workflow activities as planning operators. These operators are subsequently fed to a partial-order planner in order to find the process model as a planning solution. The continuous interplay between learning, planning and execution aims at arriving at a feasible plan by successive refinement of the operators. The approach is illustrated in two simple scenarios. The paper concludes by relating the proposed approach with previous developments in this area.
IEEE 1451 standard is intended to address the smart transducer interfacing problematic in network environments. Usually, proprietary hardware and software is a very efficient solution to implement the IEEE 1451 normat...
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IEEE 1451 standard is intended to address the smart transducer interfacing problematic in network environments. Usually, proprietary hardware and software is a very efficient solution to implement the IEEE 1451 normative, although can be expensive and inflexible. In contrast, the use of open and standardized tools for implementing the IEEE 1451 normative is proposed in this paper. Tools such as Java and Phyton programming languages, Linux, programmable logic technology, personal computer resources and Ethernet architecture were integrated in order to construct a network node based on the IEEE 1451 standards. The node can be applied in systems based on the client-server communication model. The evaluation of the employed tools and experimental results are presented
We envision users discovering suitable Web objects and configuring them on-the-fly with their desired high-level application logic, with the programming and deployment carried out entirely on the Web. Easy configurabi...
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We envision users discovering suitable Web objects and configuring them on-the-fly with their desired high-level application logic, with the programming and deployment carried out entirely on the Web. Easy configurability and interplay of Web entities implies evolution of a few common sense, yet powerful set of core primitives for effective coordination, akin in simplicity and strength to the HTTP protocol. Current Web services technology lacks Infrastructure support, theoretical sound fundamental framework for Web services coordination and composition, and easy use tools for Web application development. Our Web coordination bond system gears towards finding solutions to aforementioned research challenges.
A novel, simple and bipolar-injection based nonvolatile field-effect memory cell is demonstrated in silicon-on-insulator CMOS technology. programming time down to 8 ns are achieved together with erase times of a milli...
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A novel, simple and bipolar-injection based nonvolatile field-effect memory cell is demonstrated in silicon-on-insulator CMOS technology. programming time down to 8 ns are achieved together with erase times of a milli-second. The characteristics, compactness and compatibility with CMOS processes suggest suitability of the structure for embedded programmable and reprogrammable applications, and extensible to 3D applications. This extended abstract summarizes the technology and experimental characteristics of the device.
A single poly-silicon trench gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedd...
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A single poly-silicon trench gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedded application. The trenched floating gate (FG) combining with a deep-N-well implanted region guarantees high coupling ratio for CHEI programming and source side FN erasing operation. This cell array in a NOR-type array features fast random access capacity and IIF/sup 2/ cell size.
FELIX is a new design space exploration tool and graphical integrated development environment (IDE) for the programming of coarse-grained reconfigurable architectures. Its main and novel advantage is the use of rewrit...
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FELIX is a new design space exploration tool and graphical integrated development environment (IDE) for the programming of coarse-grained reconfigurable architectures. Its main and novel advantage is the use of rewriting rules and logical strategies for the automated generation of alternative functionally equivalent implementations from a single mathematical specification. The user selection of the rewriting logic strategies to be applied determines the resulting implementations, making it possible to quickly generate, simulate and evaluate alternative implementations that are logically equivalent. The FELIX system includes an interface to the KressArray Xplorer for hardware design-space exploration. The current version of the tool is targeted for the pact extreme processing platform (XPP), with support for additional architectures planned in future versions.
Summary form only given. The world's first microprocessor, the 4004, was co-developed by Busicom, a Japanese manufacturer of calculators, and Intel, a U.S. manufacturer of semiconductors. During the development of...
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Summary form only given. The world's first microprocessor, the 4004, was co-developed by Busicom, a Japanese manufacturer of calculators, and Intel, a U.S. manufacturer of semiconductors. During the development of a general-purpose LSI for not only desktop calculators but also other business machines, originally based on a decimal computer with a stored program method, a basic architecture of 4004 was developed in August 1969; a concrete plan for the 4004 system was finalized in December 1969; and the first microprocessor was successfully developed in March 1971. Microprocessors, which became the "technology to open up a new era", brought two outstanding impacts, "power of intelligence" and "power of computing". First, microprocessors opened up a new "era of programming" through replacing with software, the hardwired logic based on IC's of the former "era of logic". At the same time, microprocessors allowed young engineers access to "power of computing" for the creative development of personal computers and computer games, which in turn led to growth in the software industry, and paved the way to the development of high-performance microprocessors. Development engineers involved in creative development can be likened to explorers who go into unmapped territory without a compass, having hope for success and fear of failure. Also, an engineer must be armed with the firm belief that his mission is nothing but development, and must be determined to go his own way, never following another's tracks. In this paper, the birth, evolution and future of microprocessor are described. 4004 performance was only 0.06 MIPS with 2,238 transistors and 750 KHz operating frequency. Microprocessors evolved from 4 bit to 64 bit microprocessors, introducing computer technologies such as pipeline, super-pipeline, super-scalar, VLIW, cache memory, and virtual memory system. Now, it is possible to integrate 16 sets of microprocessor with 64GB of memory on the board. In 20th century, micropro
Enterprise applications need to be highly available and scalable. In the past, this has required "stateless" applications, which essentially require the application to manage its state explicitly by storing ...
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Enterprise applications need to be highly available and scalable. In the past, this has required "stateless" applications, which essentially require the application to manage its state explicitly by storing it in transactional resource managers. Despite "stateful" applications being more natural and hence easier to write and get correct, having the system manage this state automatically has been considered too difficult and too costly. The Phoenix/App system showed how to manage state in stateful applications transparently, by logging interactions between components, guaranteeing "exactly once" execution of the application. By introducing some minor restrictions on Phoenix/App components, no logging need be done for middle tier components, thus making it easy to provide both availability and scalability. Because there is no logging, the performance of failure free application executions is excellent.
An integrated fault tolerant control solution calls for a nonlinear adaptive controller with universal approximation capability and guaranteed stability. To fulfill this requirement, we propose the use of neural netwo...
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An integrated fault tolerant control solution calls for a nonlinear adaptive controller with universal approximation capability and guaranteed stability. To fulfill this requirement, we propose the use of neural networks trained online under a globalized dual heuristic programming architecture supervised by a decision logic capable of identifying controller malfunctions in early stages and providing new avenues with greater probability of convergence using information from a dynamic model bank. The classification and distinction of controller malfunctions and of the faults in the system is achieved through three independent quality indexes. Proof-of- the-concept simulations of nonlinear plants demonstrate the approach legitimacy.
The performance of an e-commerce application can be measured according to technical metrics but also following business indicators. The revenue obtained by a commercial Web application is directly related to the amoun...
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The performance of an e-commerce application can be measured according to technical metrics but also following business indicators. The revenue obtained by a commercial Web application is directly related to the amount of clients that complete business transactions. In technical terms, a business transaction is completed when a Web client successfully finishes a browsing session. In this paper we introduce a novel Web server architecture that combines the best aspects of both the multithreaded and the event-driven architectures, the two major existing alternatives, to create a server model that offers an improved performance in terms of user session completions without loosing the natural ease of programming characteristic of the multithreading paradigm. We describe the implementation of this architecture on the Tomcat 5.5 server and evaluate its performance. The obtained results demonstrate the feasibility of the hybrid architecture and the performance benefits that this model introduces for e-commerce applications.
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