Modern paper winders have hundreds of actuators and thousands of lines of programmable logic controller code. The complex structure of winder and its control software requires also new kinds of diagnostic methods. Wit...
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Modern paper winders have hundreds of actuators and thousands of lines of programmable logic controller code. The complex structure of winder and its control software requires also new kinds of diagnostic methods. With modern fault diagnostic systems, the operator can quickly and accurately identify the cause of a fault. Building up a fault diagnostic system requires usually a lot of manual work. In this paper are introduced a new multilevel product-of-sums net model and a new level-to-level-minimization algorithm, which enables to automatically transform, minimize and present programmable logic controller programs in fault diagnostic systems.
An important challenge posed by the design of open information systems concerns the choice of suitable methods to harness their complexity and to guarantee the correctness of their behaviour. In recent times, logic pr...
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An important challenge posed by the design of open information systems concerns the choice of suitable methods to harness their complexity and to guarantee the correctness of their behaviour. In recent times, logic programming has been proposed as a powerful technology, formal and declarative, for the specification and verification of agent based and open systems. In this work, we focus on the interaction design. We base our approach on a logic-based formalism, which can be used to define the semantics of agent communication languages and interaction protocols. We advocate its use within a more general framework, drawing a design methodology which encompasses the specification of the interaction space and of its desired properties, and their verification.
Summary form only given. Reconfigurable computing requires organizing computation with mixtures of processors and discrete logic thus presenting a difficult problem of hardware/software integration. An execution model...
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Summary form only given. Reconfigurable computing requires organizing computation with mixtures of processors and discrete logic thus presenting a difficult problem of hardware/software integration. An execution model and adaptation of functional programming is proposed which removes the distinction between hardware and software while offering the possibility of "correct by construction" design. The resulting language is called "V" because one way of creating it is to begin with the verifiable, synthesizable subset of Verilog, and then add functional programming features. V generates the net-list of elementary functions which are supported by an array. The compiler has stages of compilation and instantiation so that recursion can be supported in the early definition of a design. The execution model is cycle based synchronous dataflow. V syntax looks much like Verilog or C without pointers in order to facilitate adoption.
As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circ...
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As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components, called bit-slices, it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This work describes such an FPGA logic block architecture, called a multi-bit logic block, which employs configuration memory sharing to exploit datapath regularity. It is experimentally shown that, comparing to conventional FPGA logic blocks, the multi-bit logic blocks can achieve 18% to 26% logic block area reduction for implementing datapath circuits, which represents an overall FPGA area saving of 5% to 13%. A packing algorithm for the multi-bit logic block architecture is also proposed in this paper; and it is used to empirically find the best values for several important architectural parameters of the new architecture, including the most area efficient granularity values and the most area efficient amount of configuration memory sharing.
Web data extraction is a technique for extracting and integrating data from Web based semistructured data. Wrappers function like the kernel of Web data extraction systems providing information mediator between users ...
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ISBN:
(纸本)0769521258
Web data extraction is a technique for extracting and integrating data from Web based semistructured data. Wrappers function like the kernel of Web data extraction systems providing information mediator between users and a large number of heterogeneous data sources. Typically, they process semistructured documents generated from structured databases based on rules that are usually hidden to users. Much research has been done to use various methods to represent the knowledge of hidden rules and exploit techniques such as grammar induction, inductive logic programming, etc., to discover these rules that can be used by wrappers to extract data. An important property of semistructured data is its hierarchical structure. Intuitively, we can devise a method that can use this structure information to generate wrappers. We describe a Web data extraction system - WICCAP and its internal Web Data Extraction Language (WDEL) that provides unified view of Web data resources and extracted data. We describe some rule generation features of WICCAP and provide detailed description of the internal language and its implementation. We have conducted experiments to show the ease on generating wrappers with this approach.
Component middleware technologies such as the CORBA component model (CCM), J2EE (Alur et al., 2001), and .NET, were developed to address many limitations like interdependencies between services and object interfaces, ...
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Component middleware technologies such as the CORBA component model (CCM), J2EE (Alur et al., 2001), and .NET, were developed to address many limitations like interdependencies between services and object interfaces, limited re-use, of first-generation middleware technologies such as CORBA 2.x, XML, and SOAP (Snell and McLeod, 2001). These component technologies have addressed a wide range of application domains, but unfortunately for distributed real-time and embedded (DRE) systems, the focus of these technologies has been primarily on functional and not quality of service (QoS) properties. Research on QoS-aware component models such as the CIAO project (Wang et al. 2003) shows that there is a fundamental difference between configuration of functional and QoS properties even within such a unified component model: the dominant decomposition of functional properties is essentially object-oriented, while the dominant decomposition of QoS properties is essentially aspect-oriented. In this paper, we describe how a focus on aspect frameworks for configuring QoS properties both complements and extends QoS-aware component models. This paper makes three main contributions to the state of the art in DRE systems middleware. First, it describes a simple but representative problem for configuring QoS aspects that cut across architectural layers, system and distribution boundaries, which motivates our focus on aspect frameworks. Second, it provides a formalization of that problem using first order logic nfrastructure configuration logic - which both guides the design of aspect configuration infrastructure, and offers a way to connect these techniques with model-integrated computing (Ledeczi et al. 2001) approaches to further reduce the programming burden on DRE system developers. Third, it describes alternative mechanisms to ensure correct configuration of the aspects involved, and notes the phases of the DRE system lifecycle at which each such configuration mechanism is most ap
Distributed application development is overly tedious, as the dynamic composition of distributed components is hard to combine with static safety with respect to types (type safety) and data (encapsulation). Achieving...
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ISBN:
(纸本)9780769521633
Distributed application development is overly tedious, as the dynamic composition of distributed components is hard to combine with static safety with respect to types (type safety) and data (encapsulation). Achieving such safety usually goes through specific compilation to generate the glue between components, or making use of a single programming language for all individual components with a hardwired abstraction for the distributed interaction. In this paper, we investigate general-purpose programming language features for supporting third-party implementations of programming abstractions for distributed interaction among components. We report from our experiences in developing a stock market application based on type-based publish/subscribe (TPS) implemented (1) as a library in standard Java as well as with (2) a homegrown extension of the Java language augmented with specific primitives for TPS, motivated by the lacks of former implementation. We then revisit the library approach, investigating the impact of genericity, reflective features, and the type system, on the implementation of a satisfactory TPS library. We then discuss the impact of these features also on other distributed programming abstractions, and hence on the engineering of distributed applications in general, pointing out lacks of mainstream programming environments such as Java as well as .NET.
This paper concerns the implementation of adaptive controllers, in particular finite state machines (FSMs) that change their behavior at run-time. The main emphasis is to develop a technique for creating very dense-co...
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This paper concerns the implementation of adaptive controllers, in particular finite state machines (FSMs) that change their behavior at run-time. The main emphasis is to develop a technique for creating very dense-coded FSMs in order to reduce SoC programming cost. We propose an approach that combines memory-based function generators with a programmable logic to achieve proper results. For experimental tests of our FSM core we utilized a Xilinx Virtex FPGA.
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