Programmable logic controllers (PLCs) are widely used in industry. Thus PLCs usually use the IEC 1131-3 standard programming language. The ladder diagram is the most popular language which does not require a lot of th...
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Programmable logic controllers (PLCs) are widely used in industry. Thus PLCs usually use the IEC 1131-3 standard programming language. The ladder diagram is the most popular language which does not require a lot of the steps and sequences of the operation. Therefore it is difficult to understand the program structure and developing the system. The Petri net is a graphical model that can explain the system operation easily and clearly. This paper presents the transformation structures from Petri nets to ladder diagram and possible implementation to control the process through the PLC's input and output.
The required 1 MHz/spl sim/30 MHz 100 Hz step frequency sine signal is obtained by frequency mixing between 2 kHz and 100 Hz step sine signals generated by a voltage-controlled oscillator, MC1648, that is controlled b...
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ISBN:
(纸本)0780384040
The required 1 MHz/spl sim/30 MHz 100 Hz step frequency sine signal is obtained by frequency mixing between 2 kHz and 100 Hz step sine signals generated by a voltage-controlled oscillator, MC1648, that is controlled by a PLL, MC145146. The MC145146 is a PLL large-scale IC using a double mode frequency synthesizer, and the frequency setting is realizing by programming a 4 bit data bit, 3 bit address code and 1 bit signal selection bit. The MC145146 includes a 12 bit programmable reference counter (frequency dividing range: 3/spl sim/ 095), a 10 bit main counter (counting range: A=0/spl sim/127), a two phase discriminator, double mode control logic and flip-latch which is used to receive input data and address code. Matched with a double mode frequency demultiplier, a 4 Hz frequency resolution can be obtained.
This work focuses on improving network management and monitoring by the adoption of artificial intelligence techniques. In order to allow automated reasoning on networking concepts, we defined an accurate ontological ...
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This work focuses on improving network management and monitoring by the adoption of artificial intelligence techniques. In order to allow automated reasoning on networking concepts, we defined an accurate ontological model capable of describing as better as possible the networking domain. The thorough representation of the domain knowledge is used by a logical reasoner, which is an expert system capable of performing high-level management tasks.
System and circuit design can be considered as planning problems, where resources are deployed in time and space to meet a given goal. Recent and continuing developments in the size of SAT problems and other AR proble...
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System and circuit design can be considered as planning problems, where resources are deployed in time and space to meet a given goal. Recent and continuing developments in the size of SAT problems and other AR problems that can be solved with off-the-shelf tools leads us to consider their direct use in system design. In this paper, we start to tackle the design of small hardware subsystems and the generation of glue logic between systems by asking a SAT solver to generate the programming bit stream for a fictional gate array.
This paper brings together two recent contributions to the area of declarative agent-oriented programming, made feasible in practice by the recent introduction of an interpreter for a BDI programming language. The wor...
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This paper brings together two recent contributions to the area of declarative agent-oriented programming, made feasible in practice by the recent introduction of an interpreter for a BDI programming language. The work on Coo-BDI has proposed an approach to plan exchange which applies to BDI agents in general. The other contribution is the introduction of special illocutionary forces for plan exchange between AgentSpeak agents. This has been implemented in Jason, an interpreter for an extended version of that language. This paper shows how the elaborate plan exchange mechanism of Coo-BDI can be used by AgentSpeak agents implemented with Jason. It also discusses an application on PDA-based multi-media presentations in museum visits for which plan exchange is relevant.
In this paper, we present a novel graph-oriented approach to architecting and modeling CORBA-based distributed applications. It provides higher-level abstractions for the architecture description of CORBA-based distri...
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ISBN:
(纸本)0769522165
In this paper, we present a novel graph-oriented approach to architecting and modeling CORBA-based distributed applications. It provides higher-level abstractions for the architecture description of CORBA-based distributed applications. In the proposed model, the software architecture of a CORBA-based distributed application is described as a logical graph separated from the programming of the constituent components of the application. It also provides more powerful support for specifying dynamism in software architecture and simplification of CORBA programming.
Nominal logic is a theory of names and binding based on the primitive concepts of freshness and swapping, with a self-dual N- (or "new")-quantifier, originally presented as a Hilbert-style axiom system exten...
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Nominal logic is a theory of names and binding based on the primitive concepts of freshness and swapping, with a self-dual N- (or "new")-quantifier, originally presented as a Hilbert-style axiom system extending first-order logic. We present a sequent calculus for nominal logic called fresh logic, or FL, admitting cut-elimination. We use FL to provide a proof-theoretic foundation for nominal logic programming and show how to interpret FO/spl lambda//spl nabla/, another logic with a self-dual quantifier, within FL.
Summary form only given. Conforming to the underlying memory consistency rules is a fundamental requirement for implementing shared memory systems and developing multiprocessor programs. In order to promote understand...
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Summary form only given. Conforming to the underlying memory consistency rules is a fundamental requirement for implementing shared memory systems and developing multiprocessor programs. In order to promote understanding and enable automated verification, it is highly desirable that a memory model specification be both declarative and executable. We present a specification framework called Nemos (Nonoperational yet Executable Memory Ordering Specifications), which supports precise specification and automatic execution in the same framework. We employ a uniform notation based on predicate logic to define shared memory semantics in an axiomatic as well as compositional style. We also apply constraint logic programming and SAT solving to make the axiomatic specifications executable for memory model analysis. To illustrate our approach, we formalize a collection of classical memory models, including sequential consistency, coherence, PRAM, causal consistency, and processor consistency.
Multicontext field programmable gate arrays (FPGAs) are excellent devices to use in reconfigurable computing systems for boosting performance. In addition, multicontext devices can save space compared to the conventio...
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Multicontext field programmable gate arrays (FPGAs) are excellent devices to use in reconfigurable computing systems for boosting performance. In addition, multicontext devices can save space compared to the conventional FPGAs because they store more programming data per area. However, multicontext FPGAs suffer the same long configuration delays as conventional FPGAs, and this limits performance in some situations. To solve that problem, we introduce a new FPGA called PRMC. The PRMC FPGA is an enhanced multicontext design that has partially reconfigurable contexts and additional features to reduce the configuration overhead. As a result, PRMC configures faster than present multicontext FPGAs, while enjoying the same area benefit. This paper describes the architecture of our PRMC FPGA.
Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, t...
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Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C67J3 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.
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