A modified Flash-EEPROM device is presented. This device operates as a non-volatile programmable pass transistor. Program and erase, operations are performed on a Flash-EEPROM cell coupled to a pass-transistor. Writte...
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A modified Flash-EEPROM device is presented. This device operates as a non-volatile programmable pass transistor. Program and erase, operations are performed on a Flash-EEPROM cell coupled to a pass-transistor. Written and erased states of the flash cell correspond to the open and close states of the pass-transistor respectively. The Flash-programmable pass transistor (FPT) was developed for multi-context programmable-logic, and it was realized in a technology for embedded Flash-EEPROM NOR memory. No additional process steps are required. This novel device has the same program and erasing behavior as the standard Flash-EEPROM cell, measurements are reported for a 0.18 /spl mu/m technology implementation.
Iwaki Meisei University, a popular university in Japan, has developed e-Learning oriented programming Courseware for freshmen using the authoring tool Hiplus, Hitachi Ltd., Japan, at the Department of Electronics and ...
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Iwaki Meisei University, a popular university in Japan, has developed e-Learning oriented programming Courseware for freshmen using the authoring tool Hiplus, Hitachi Ltd., Japan, at the Department of Electronics and Computer Science. Department freshmen are required to use this programming Courseware. This courseware consists of two parts: specification of requirement and verification of program validity. Both parts address the need for support by logical thinking in addition to production of software documents by a natural language. Using it, a modern programmer can use a dedicated algorithm which handles a newly developed object once a software requirement has been formally specified Moreover freshmen are able to assess their own learning progress due to graded exercises configured in the programming Courseware.
XML is designed to structure data for exchange. It is also a new trend to use XML to encode knowledge on the Web. An important project for this purpose is the semantic Web of W3C. They proposed several specifications,...
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ISBN:
(纸本)0780377249
XML is designed to structure data for exchange. It is also a new trend to use XML to encode knowledge on the Web. An important project for this purpose is the semantic Web of W3C. They proposed several specifications, including RDF/RDFS and OWL, for knowledge representation. In the architecture of SW, they proposed XML for the syntax layer, RDF/RDFS for the semantics layer, and OWL for the ontology layer. However, languages for the logic layer and proof layer are not yet defined. We propose a different approach for knowledge representation and reasoning. We define a logic-based framework to transform XML documents into logical facts, and to reason about these facts. The transforming and reasoning processes are based on a logic programming language, path inference language (PIL), which is specifically designed for tree-structure documents like XML. People may write a PIL program to extract logical facts from XML documents, and the extracted logical facts are imported into a logic-based ontology in PIL for reasoning. Based on PIL, we intend to develop a simple and powerful framework for people to interpret the semantics of XML easily.
The paper describes a methodological framework that aims to apply formal design and verification techniques to the domain of logic control and supervision for manufacturing systems. The methodology is based on an obje...
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The paper describes a methodological framework that aims to apply formal design and verification techniques to the domain of logic control and supervision for manufacturing systems. The methodology is based on an object-oriented approach, supported by a syntactical and semantical adaptation of the semi-formal software specification languages UML and statecharts. The modeling languages have been subsequently formalized, according to a semantics that take into account the concepts described in the IEC 61131-3 standard for industrial controllers programming, in order to prove correctness properties expressed in the temporal logic CTL. The verification process is performed by means of the model-checking tool SMV.
In todays deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field programmable gate arrays (FPGAs), interconnect...
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In todays deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field programmable gate arrays (FPGAs), interconnect delays are crucial, since they can easily vary by orders of magnitude. Many existing performance-directed retiming methods use simple delay models which either neglect routing delays or use inaccurate delay estimations. In this paper, we propose a retiming approach which overcomes the problem of inaccurate delay models. Our retiming technique uses delay information extracted from a fully placed and routed design and takes account of register timing requirements. By applying physical constraints, we ensure that the delay information remains valid during retiming. In our experiments, we achieved up to 27% performance improvement.
Resolution-based automated reasoning theory is an important and active research field in artificial intelligence. It is used to judge the satisfiability of any logic formula. With the development of classical and non-...
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ISBN:
(纸本)0780378652
Resolution-based automated reasoning theory is an important and active research field in artificial intelligence. It is used to judge the satisfiability of any logic formula. With the development of classical and non-classical logic, the resolution theory and method based on different logic system has been discussed widely and deeply. In the present paper, a new resolution principle by using ultrafilter in LP/sub 6/(X) is put forward. Different from existed method of resolution, this resolution in this paper is based on ultrafilter of lattice implication algebra. Because of LP/sub 6/(X) is a non-chain, non-boolean and non-well-ordered algebra structure, resolution based on LP/sub 6/(X) can be the theoretical foundation of resolution on lattice-valued truth-field. Accordingly, the research in this paper is helpful supported for the application of intelligent reasoning system based on lattice-valued logic.
作者：
Maes, SHIBM Corp
Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA
For the mobile Internet, new content and applications are developed with the intent of delivering it through many different channels with different characteristics. Therefore, such content and applications must be ada...
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Despite the advances in software engineering since 1968, current methods for going from a set of functional requirements to a design are not as direct, repeatable and constructive as we would like. Progress with this ...
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Despite the advances in software engineering since 1968, current methods for going from a set of functional requirements to a design are not as direct, repeatable and constructive as we would like. Progress with this fundamental problem is possible once we recognize that individual functional requirements represent fragments of behavior, while a design that satisfies a set of functional requirements represents integrated behavior. This perspective admits the prospect of constructing a design out of its requirements. A formal representation for individual functional requirements, called behavior trees makes this possible. Behavior trees of individual functional requirements may be composed, one at a time, to create an integrated design behavior tree. From this problem domain representation it is then possible to transition directly and systematically to a solution domain representation of the component architecture of the system and the behavior designs of the individual components that make up the system - both are emergent properties.
This study examined the effectiveness of pair programming in four lecture sections of a large introductory programming course. We were particularly interested in assessing how the use of pair programming affects stude...
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This study examined the effectiveness of pair programming in four lecture sections of a large introductory programming course. We were particularly interested in assessing how the use of pair programming affects student performance and decisions to pursue computer science related majors. We found that students who used pair programming produced better programs, were more confident in their solutions, and enjoyed completing the assignments more than students who programmed alone. Moreover, pairing students were significantly more likely than non-pairing students to complete the course, and consequently to pass it. Among those who completed the course, pairers performed as well on the final exam as non-pairers, were significantly more likely to be registered as computer science related majors one year later, and to have taken subsequent programming courses. Our findings suggest that not only does pairing not compromise students' learning, but that it may enhance the quality of their programs and encourage them to pursue computer science degrees.
This paper presents a precise specification matching, both structural and functional matching, to explore component retrieval and adaptation. Structural matching is used to check adaptability, while functional matchin...
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ISBN:
(纸本)0780382420
This paper presents a precise specification matching, both structural and functional matching, to explore component retrieval and adaptation. Structural matching is used to check adaptability, while functional matching is used to ensure the proper functionality. We introduce attributed labeled transition systems (ALTS) to formally specify component structures and functionalities. Automated component adaptation is facilitated by a matching tool implemented in a tabled logic programming environment, which provides distinct advantages for rapid prototyping and implementation. Examples are given to illustrate how the concrete adapter is derived automatically from specification matching.
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