检索结果-内蒙古大学图书馆

NEW APPROACH FOR THE ORDERING OF GATE PERMUTATION IN ONE-DIMENSIONAL logic-arrays

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1995年第1期142卷 90-96页

作者： LEE, J CHOU, JH FU, SL NATL CHENG KUNG UNIV DEPT ENGN SCITAINAN 70101TAIWAN

The one-dimensional gate permutation problem is transferred into a new one of achieving an optimum gate permutation under the constraint of a predetermined adjustable maximum number of tracks. A fast and efficient constructive algorithm is proposed to solve it. The algorithm has the advantage of uniformly distributing the local congestion so that optimum permutation with the required track number can be obtained. The experimental results show that it is a fast algorithm and gives better solutions than other constructive algorithms. Moreover, it can be used as an improvement algorithm by using a modified ratio-cut technique. The improvement algorithm iteratively improves the previous solutions, and thus results comparable to the simulated annealing approach can be obtained in less CPU time.

关键词： GATE PERMUTATION logic arrays

来源：评论

学校读者我要写书评

暂无评论

A DESIGN OF PROGRAMMABLE logic-arrays WITH RANDOM PATTERN-TESTABILITY

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第1期7卷 5-10页

作者： FUJIWARA, H Department of Electronics and Communications Meiji University Japan

A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array of the PLA. Several variations of the proposed approach are presented. The probability of fault detection and the test length are examined for both stuck-type and crosspoint-type faults to estimate the fault coverage achievable with the random patterns.< >

关键词： Programmable logic arrays logic design Circuit testing logic testing Circuit faults Built-in self-test Fault detection Software testing Sequential analysis logic arrays

来源：评论

学校读者我要写书评

暂无评论

LILA - LAYOUT GENERATION FOR ITERATIVE logic-arrays

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1995年第11期14卷 1359-1369页

作者： WU, QH CHEN, CYR CARLSON, BS SYRACUSE UNIV SYRACUSE NY 13244 USA SUNY STONY BROOK STONY BROOK NY 11794 USA

A CAD tool, LILA, that generates layouts of both one-dimensional and two-dimensional iterative logic arrays, described in VHDL or schematic structures, is presented, Such a tool is very important because in current industry, the generation of high density iterative logic arrays (such as data path in microprocessors) is still mainly performed manually, and is a major bottleneck of the design, In LILA, interconnections between modules (i.e., cells) of the array do not need to be between adjacent modules and functions of modules of the array do not need to be identical, Regularity in module functions and interconnections between modules are automatically extracted by the tool, Based on interconnection wire length between modules, layouts of modules and interconnections are optimized in a single step, The signals in each array module are generated in such a way that signals in adjacent modules are perfectly aligned and connected by module abutments, As no global routing or channel routing between modules are necessary, the total layout area and propagation delay between modules are minimal. The proposed system is especially useful for data path modules, bit-level systolic arrays, storage devices, and many other regular structures, and has been actually implemented in a design environment, Extensive experiments have shown that the system has a very good performance and produces layouts of very high density, The tool takes about 1.6 CPU seconds to generate an eight-by-eight array divider on a SUN SPARC station II.

关键词： logic arrays Routing Integrated circuit interconnections logic design Microprocessors Signal generators Systolic arrays logic devices Associate members Wire

来源：评论

学校读者我要写书评

暂无评论

SELF-CHECKING logic-arrays

引用

MICROPROCESSORS AND MICROSYSTEMS 1989年第4期13卷 281-290页

作者： NICOLAIDIS, M COURTOIS, B IMAG/TIM3 46 Avenue Félix Viallet 38031 Grenoble Cedex France

Self-checking blocks may be used to ensure concurrent error detection in integrated circuits. On the other hand, logic arrays such as PLAs, ROMs and RAMs are essential to circumvent the increasing complexity of VLSI circuits. Efficient self-checking schemes for logic arrays are therefore essential for concurrent error detection in VLSI circuits. The paper describes schemes that incur low area overhead.

关键词： logic arrays microsystems self-checking circuits VLSI

来源：评论

学校读者我要写书评

暂无评论

A HEURISTIC ALGORITHM FOR ORDERING THE COLUMNS IN ONE-DIMENSIONAL logic-arrays

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第5期8卷 547-562页

作者： HONG, YS PARK, KH KIM, M Department of Electrical Engineering Korea Advanced Institute of Science and Technology Seoul South Korea

The authors focus on the ordering of the columns to minimize the necessary number of tracks in one-dimensional logic array. They use a column-orientation approach to this problem. Each net is converted into a complete graph (or clique). The weighted graph using such topological transformation is unique. The necessary number of tracks can be evaluated by the cut of the two seeds of orderings, the left seed vertex and the right seed vertex. The authors find the minimal track assignments by minimizing the cut of the seed vertex. Additionally, a useful concept called the overriding property is introduced. It determines the local optimal assignments for two or more columns with the above property. The author's algorithm works well with either a uni- or bidirectional approach to select the seed of ordering. Results obtained by the proposed algorithm and the simulated annealing approach are compared.< >

关键词： Heuristic algorithms logic arrays Wire CMOS technology CMOS logic circuits Wiring Simulated annealing MOS devices Adders logic design

来源：评论

学校读者我要写书评

暂无评论

CONCURRENT ERROR-DETECTION IN HIGHLY STRUCTURED logic-arrays

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1987年第4期22卷 583-594页

作者： FUCHS, WK CHEN, CYR ABRAHAM, JA Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana IL USA

Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.

关键词： logic arrays Fault detection Circuit faults Programmable logic arrays logic devices Encoding Very large scale integration Testing Decoding Read only memory

来源：评论

学校读者我要写书评

暂无评论

ENHANCING RANDOM-PATTERN COVERAGE OF PROGRAMMABLE logic-arrays VIA MASKING TECHNIQUE

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第9期8卷 1022-1025页

作者： FUJIWARA, H Department of Computer Science Meiji University Japan

A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is presented. The proposed design is realized with low area overhead by adding two mask arrays to the AND and OR arrays of the PLA. An experiment was performed to demonstrate the effect of the masking technique. In the experiment, eight large PLAs were modified by adding mask arrays of various sizes; fault simulation with random patterns for modified and unmodified PLAs was then carried out to obtain random-pattern test coverage curves. Fault coverage can be significantly enhanced via the proposed masking technique with very low area overhead.< >

关键词： Programmable logic arrays Circuit faults Circuit testing Built-in self-test Decoding logic testing logic arrays logic design Very large scale integration MOS devices

来源：评论

学校读者我要写书评

暂无评论

A TESTABLE DESIGN OF ITERATIVE logic-arrays

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 1981年第11期28卷 1037-1045页

作者： PARTHASARATHY, R REDDY, SM UNIV IOWA DEPT ELECT & COMP ENGNIOWA CITYIA 52242

Testable design of unilateral iterative logic arrays (ILA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-stepC-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number(\\leq 4)of columns and a row so that a faulty cell can be located by a test of length proportional to\\log_2 p, wherepis the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell. A set of simpler sufficient conditions are given for the testability of two-dimensional arrays. It is shown that these conditions ensure that all possible input states can be applied to every cell in an array of arbitrary dimensions.

关键词： logic testing logic arrays logic design Circuit faults Circuit testing Fault detection Sufficient conditions Fabrication Electrical fault detection Fault diagnosis

来源：评论

学校读者我要写书评

暂无评论

Quasi-Adiabatic logic arrays for Silicon and Beyond-Silicon Energy-Efficient ICs

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2016年第12期63卷 1111-1115页

作者： Tenace, Valerio Calimera, Andrea Macii, Enrico Poncino, Massimo Politecn Torino Dept Control & Comp Engn I-10129 Turin Italy

This brief describes a novel integration strategy that aims at bringing adiabatic computation to large scale integration. The proposed design solution, built upon logic primitives packed into regular arrays, the quasi-adiabatic-logic-arrays (QALAs), is well suited not just for today's silicon transistors but also for emerging devices. QALAs are indeed a viable path toward the integration of ultra-low power ICs using devices with a gapless energy spectrum, graphene p-n junctions in particular. The design of QALA circuits is supported by a dedicated RTL-to-device design framework whose kernel consists of a new area/delay-driven logic synthesis and optimization engine. Simulation results conducted on several benchmarks mapped both onto silicon (using 40 nm MOSFETs) and graphene (using electrostatically controlled p-n junctions) show the proposed methodology provides adiabatic logic circuits with a power-delay-product that is one order of magnitude smaller than that of state-of-the-art adiabatic circuits implemented using pass-transistor logic and conventional logic synthesis flows.

关键词： Adiabatic beyond-CMOS circuit synthesis CMOS logic arrays low-power

来源：评论

学校读者我要写书评

暂无评论

A FLEXIBLE APPROACH TO EMITTER-COUPLED logic arrays

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1969年第1期SC 4卷 13-&页

作者： DAGOSTIN.MV FELLER, A Special Electronic Components Division RCA Somerville NJ USA RCA Advanced Technology Division EDP Camden NJ USA

The ECCSL arrays have been successfully fabricated using two levels of metalization on 120 by 120-mil chips. The yield, fabrication, and performance studies of these arrays, while not yet complete, indicate that current mode logic arrays of 10 to 30 gates are entirely feasible. This is especially true if the size of the chips are reduced as much as possible (preferably below 0.10 by 0.10 inch.) Indications are that arrays with relatively low gate counts (10 to 30 gates) greatly reduce the testing problems usually associated with array technology.

关键词： logic arrays Integrated circuit manufacture logic devices Fabrication logic functions Electronic components Registers Pins Resistors Data processing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：