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检索条件"主题词=Logic arrays"

共 2662 条记录，以下是91-100 订阅

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Design for variability in CMOS logic circuits: Uncommitted motif arrays (UMAs)

Design for variability in CMOS logic circuits: Uncommitted m...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Sonia H. Paluchowski Caldwell David R. S. Cumming Department of Electronics & Electrical Engineering University of Glasgow Glasgow UK

ISBN: (纸本)9781424438273

Systematic and statistical variability in digital design is becoming increasingly important, and this will be even more pronounced in sub-45 nm technologies. We propose the use of uncommitted arrays of digital sub-blocks, motifs, as the basic building block for CMOS logic. These uncommitted motif arrays maximize functional flexibility, minimize routing complexity, and increase tolerance to systematic variability. The analytical selection of motifs is presented along with a design of a proposed array. We show prototypical design based on the proposed methodology to illustrate the improved regularity of designs, and the resulting routing efficiency compared to traditional uncommitted logic arrays.

关键词： CMOS logic circuits logic arrays logic design Resource description framework Routing Software libraries logic devices CMOS technology Prototypes Integrated circuit interconnections

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Implementing logic in FPGA embedded memory arrays: architectural implications

Implementing logic in FPGA embedded memory arrays: architect...

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Custom Integrated Circuits Conference (CICC)

作者： S.J.E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

It has become clear that embedded memory arrays will be essential in future FPGAs. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. In this paper, we explore how the depth, width, and flexibility of the embedded arrays affect their ability to implement logic. It is shown that each array should contain between 512 and 2048 bits, and should have a word width that can be configured as 1, 2, 4, or 8.

关键词： logic arrays Field programmable gate arrays Random access memory Read-write memory Lattices logic design logic circuits Space exploration Service oriented architecture System-on-a-chip

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Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques for 2-3GHz on-chip cache arrays in microprocessors on 90nm logic technology

Bitline leakage compensation (BLC) and leakage reduction (BL...

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Symposium on VLSI Circuits

作者： M. Khellah Y. Ye D. Somasekhar D. Casper B. Bloechel T. Nguyen G. Dermer K. Zhang G. Pandya A. Farhang V. De Circuits Research Intel Hillsboro OR USA LTD Advanced Design Group Intel Hillsboro OR USA Desktop Products Group Intel Hillsboro OR USA

Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz fo... 详细信息

关键词： logic arrays Microprocessors logic testing Calibration logic design Frequency Delay Voltage logic circuits Circuit testing

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Design of fault-tolerant cellular arrays on multiple-valued logic

Design of fault-tolerant cellular arrays on multiple-valued ...

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International Symposium on Multiple-Valued logic

作者： N. Kamiura Y. Hata K. Yamato Faculty of Engineering Himeji Institute of Technology Himeji Japan

This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array.< >

关键词： logic arrays Fault tolerance logic design Circuit faults Switches Circuit testing Buildings Very large scale integration Design for testability Iterative algorithms

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An Integrated logic/VMOS Driver System for LED arrays

An Integrated Logic/VMOS Driver System for LED Arrays

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European Conference on Solid-State Circuits (ESSCIRC)

作者： J.H. van Wyngaarden GEC-Marconi Hirst Research Centre Wembley Middlesex UK

Integrated combinations of VMOS power transistors with VMOS and NMOS logic have given a minimum component LED matrix addressing system. The matrix size remains flexible with chip layout optimised for hybridisation.

关键词： logic arrays Light emitting diodes Transmission line matrix methods Driver circuits Space technology MOSFETs Clocks MOS devices logic circuits Switches

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Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

Fault-tolerant multi-level logic decoder for nanoscale cross...

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IEEE International Conference on Computer-Aided Design

作者： M. Haykel Ben Jamaa David Atienza Giovanni De Micheli Kirsten E. Moselund Didier Bouvet Adrian M. Ionescu Yusuf Leblebici Integrated Systems Laboratory (LSI) EPF Lausanne Lausanne Switzerland Electronics Laboratory LEG EPF Lausanne Lausanne Switzerland DACYA Complutense University of Madrid Madrid Spain Electronics Laboratory EPF Lausanne Lausanne Switzerland Microelectronic Systems Laboratory (LSM) EPF Lausanne Lausanne Switzerland

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages ( V T ), which is enabled by our underlying technology. We define two types of multi-valued decoders and model the defects they undergo due to the V T variation. Multi-valued hot decoders yield better area saving than n -ary reflexive codes (NRC), and under severe conditions, NRC enables a non-vanishing part of the code space to recover. There are many combinations of decoder type and number of V T 's yielding equal effective memory capacities. The optimal choice saves area up to 24%. We also show that the precision of the addressing voltages for decoders with unreliable V T 's is a crucial parameter for the decoder design and permits large savings in memory area.

关键词： logic arrays Fault tolerance Decoding Nanowires Circuits Silicon on insulator technology Double-gate FETs Laboratories CMOS technology Switches

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The Exemplar logic synthesis system: a logic synthesis tool for field programmable gate arrays

The Exemplar Logic synthesis system: a logic synthesis tool ...

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Annual IEEE International Conference and Exhibit ASIC

作者： M. Ligthart R. Ranauro Exemplar Logic Inc. Berkeley CA USA

High density programmable logic devices require dedicated synthesis algorithms to maximize the utilization of the device resources. The authors discuss the impact of device architectures on logic synthesis algorithms, and show how device specific optimization allows designers to design for multiple architectures from a common design description. The Exemplar logic synthesis system combines industry standard design entry methods with architecture specific optimization algorithms. This power lets designers easily migrate PLD, FPGA, or ASIC designs to FPGAs or ASICs, and gives designers using top-down design techniques the flexibility to explore speed versus area tradeoffs between FPGAs and ASICs early in the design cycle.< >

关键词： Programmable logic arrays Field programmable gate arrays logic devices Programmable logic devices Algorithm design and analysis logic programming logic design Application specific integrated circuits Design optimization logic arrays

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Incorporating logic Operations into SRAM arrays: A study of IMC Architectures and Their Implications

Incorporating Logic Operations into SRAM Arrays: A study of ...

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Smart Electronics and Communication Systems (ISENSE), International Conference on

作者： Safvan C K Bristo C J Suryagayatri Thangalazhi Goutham S Kumar Adersh V R Department of Electronics and Communication Engineering College of Engineering Trivandrum India

ISBN: (数字)9798331528126

ISBN: (纸本)9798331528133

In-memory computing (IMC) rethinks data processing, crucial for speed and energy efficiency. It aims to address issues of traditional computing, separating memory and processors, which increases costs and energy usage. This study focuses on using SRAM cells for IMC, integrating basic operations to reduce power consumption. Asymmetric Sense Amplifiers (ADSA) play a key role in logic circuits, enhancing accuracy under low power. The research explores how logic operations in memory can enhance computational abilities, providing efficient low-power systems. Implementation challenges are discussed, showcasing IMC's potential in modern electronics.

关键词： Electric potential Program processors Power demand Costs SRAM cells In-memory computing Data processing Energy efficiency logic logic arrays

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Intelligent Fault Detection and Shading Analysis in Photovoltaic arrays: A Fuzzy logic Approach for Enhanced Performance and Reliability

Intelligent Fault Detection and Shading Analysis in Photovol...

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Computational Intelligence for Green and Sustainable Technologies (ICCIGST), International Conference on

作者： S. Vijaya Madhavi K. Ramalingeswara Prasad Bankaru Sonia Madhavi Mallam Jami Venkata Suman K.B. Anusha Department of EEE Malla Reddy Engineering College for Women Telangana India Department of EEE Lakkireddy Bali Reddy College of Engineering Mylavaram Andhra Pradesh India Department of EEE Vignan’s Institute of Information Technology (A) Duvvada Andhra Pradesh India Department of ECE PES Institute of Technology and Management Shivamogga Karnataka India Department of ECE GMR Institute of Technology Rajam Andhra Pradesh India Department of CSE Aditya Institute of Technology and Management Tekkali Andhra Pradesh India

ISBN: (数字)9798350381887

ISBN: (纸本)9798350381894

Among various renewable energy resources, solar power holds tremendous potential to address the challenge of depleting non-renewable energy sources. In contemporary times, an increasing number of households are embracing photovoltaic (PV) systems. As the adoption of these systems grows, it becomes crucial to monitor them effectively to safeguard against weather and atmospheric conditions. This study proposes an innovative technique for fault detection in photovoltaic arrays through the application of a fuzzy logic controller. Utilizing a simulation model, the voltage and current variations are analyzed under eight distinct fault scenarios, including open circuit, short circuit, partial shading, bypass diode failure, snow accumulation, and faults such as bird droppings or tree leaves. The simulated attributes are then input into the fuzzy logic controller, enabling it to predict the type of fault occurring within or between photovoltaic modules.

关键词： Fuzzy logic Fault diagnosis Fault detection Atmospheric modeling Electrical fault detection Solar panels Integrated circuit reliability logic arrays Monitoring Testing

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Flexible Memory, Bit-Passing and Mixed logic/Memory Operation of two Intercoupled FeFET arrays

Flexible Memory, Bit-Passing and Mixed Logic/Memory Operatio...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Evelyn T. Breyer Halid Mulaosmanovic Stefan Slesazeck Thomas Mikolajick NaMLab gGmbH Nöthnitzer Straße 64a 01187 Dresden Germany Nanoelectronic Materials Technische Universität Dresden 01069 Dresden Germany

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Recently, memory and logic were brought into closer vicinity by introducing logic-in-Memory circuits based on ferroelectric FETs (FeFET), where the FeFET not only stores logic values in its ferroelectric layer, but also performs logic operations of externally applied inputs with these internally stored values. As one reason for using these structures is to overcome the von-Neumann bottleneck, their logic readout gained a lot of attention, while the storage of the calculated outputs was neglected. In this paper, we propose to utilize two intercoupled memory arrays for this purpose. Between these, three operation modes are possible: pure memory operation, a passing of bits through the structure (logic mode), and conducting a logic operation in cells of the first memory array, whose result is stored in the cells of the second memory array, directly combining the logic and memory capability of these structures. For the latter, we suggest a suitable operation scheme. Electrical measurements of 28nm HKMG FeFET test structures based on hafnium oxide (HfO 2 ) confirm the feasibility of the proposed logic/memory mixed mode.

关键词： logic gates logic arrays Field effect transistors Clocks Hafnium compounds Voltage measurement Electric potential

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