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Visions for application development on hybrid computing systems

PARALLEL COMPUTING 2008年第4-5期34卷 201-216页

作者： Chamberlain, Roger D. Lancaster, Joseph M. Cytron, Ron K. Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

Hybrid computing systems (incorporating FPGAs, GPUs, etc.) have received considerable attention recently as an approach to significant performance gains in many problem domains. Deploying applications on these systems, however, has proven to be difficult and very labor intensive. in this paper we review the current state of practice for application development on hybrid systems. We also present our vision of the application development languages and tools that we believe would greatly benefit the process of designing, implementing, and deploying applications on hybrid systems. (C) 2008 Elsevier B.V. All rights reserved.

关键词： coordination languages chip multiprocessors field-programmable logic arrays graphics processing units

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Adaptive multiuser online reconfigurable engine

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IEEE DESIGN & TEST OF COMPUTERS 2000年第1期17卷 53-67页

作者： Rakhmatov, DN Vrudhula, SBK Brown, TJ Nagarandal, A Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

We describe an adaptive multiuser computing platform under development. We focus on the two major components of its software infrastructure: hardware clustering and I/O scheduling.

关键词： Engines Resource management Processor scheduling Hardware Microprocessors Runtime logic arrays Adaptive arrays Dynamic scheduling Reconfigurable logic

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Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1999年第1期46卷 151-158页

作者： Maeda, S Hirano, Y Yamaguchi, Y Iwamatsu, T Ipposhi, T Ueda, K Mashiko, K Maegawa, S Abe, H Nishimura, T Mitsubishi Elect Co ULSI Dev Ctr Itami Hyogo 664 Japan Mitsubishi Elect Co Kita Itami Works Itami Hyogo 664 Japan Mitsubishi Elect Co Syst LSI Dev Ctr Itami Hyogo 664 Japan

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, "substrate bias" is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating bddy-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits.

关键词： Electric breakdown MOSFET circuits Semiconductor device breakdown Silicon on insulator technology FETs Analytical models Character generation Electrodes logic circuits logic arrays

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DEVICE INTERCONNECTION TECHNOLOGY FOR ADVANCED THERMAL CONDUCTION MODULES

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IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY 1992年第4期15卷 432-437页

作者： RAY, SK BECKHAM, KF MASTER, RN General Technology Division East Fishkill Facility IBM Corporation Hopewell Junction NY USA

Area array solder bumps on silicon devices known as controlled collapse chip connection (C4) balls have been successfully used in terminating logic and memory devices to ceramic substrates in numerous IBM products over the last two decades. With the recent announcement of the IBM System 390/ES 9000 series of mainframe computers, this highly reliable chip termination technology has been extended to a new height of both interconnection density and total number of chip I/O connections per module. In addition, in the models 820 and 900 of the ES 9000 series, a totally new materials set, namely glass-ceramic with copper internal metallization along with thin film redistribution wiring on the top surface, has been introduced for multilayered ceramic substrates. In this paper, key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules (ATCM's). These modules also have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70 000 solder balls per module is discussed.

关键词： Thermal conductivity Substrates logic arrays Ceramics Silicon devices logic devices Conducting materials Inorganic materials Copper Metallization

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DECOMPOSITIONS OF logicAL FUNCTIONS USING MAJORITY DECISION ELEMENTS

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IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS 1964年第6期EC13卷 698-&页

作者： TOHMA, Y Electronic Engineering Department Tokyo Institute of Technology Tokyo Japan

A method of decomposing logical functions using three input majority gates is given. This method requires that at least one of the inputs to the gate be specified, and from this the other inputs may be found. For unate functions one of the variables may be completely separated at each level. A method using a Karnaugh map is proposed for finding the best function to use as the specified input, which will make the other inputs to the majority gate easier to synthesize.

关键词： logic arrays Computer aided manufacturing Sequential circuits Contracts Network synthesis Adaptive systems Mathematics Instruments Diodes

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THE EFFECT OF logic BLOCK ARCHITECTURE ON FPGA PERFORMANCE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1992年第3期27卷 281-287页

作者： SINGH, S ROSE, J CHOW, P LEWIS, D UNIV TORONTO DEPT ELECT ENGNTORONTO M5S 1A4ONTARIOCANADA

This paper explores the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGA's that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The primary reason is that these blocks can implement typical logic using the fewest levels of logic blocks, and thus incur a small number of stages of the slow programmable routing present in all FPGA's. The secondary reason is that their inherent combinational delay is not excessive. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay.

关键词： Field programmable gate arrays Delay Routing Programmable logic arrays logic circuits logic arrays Multiplexing Table lookup Manufacturing logic devices

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P-OPALS - PURE OPTICAL-PARALLEL ARRAY logic SYSTEM

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PROCEEDINGS OF THE IEEE 1994年第11期82卷 1668-1677页

作者： TANIDA, J KONISHI, T ICHIOKA, Y Department of Applied Physics Faculty of Engineering Osaka University Suita Osaka Japan

In this paper, we present an all-optical version of the OPALS, called P-OPALS, as an instance of a pure optical computing system to clarify its potential capabilities. Before discussing the P-OPALS, basic concepts of OAL and the OPALS are explained. On the P-OPALS, utilized techniques and an experimental system are presented along with experimental results. Finally, processing capability of the P-OPALS is estimated in terms of data number and processing capacity.

关键词： logic arrays Optical arrays Optical computing High speed optical techniques Optical feedback Nonlinear optics Computer architecture Parallel processing Optical interconnections Concurrent computing

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30-PS 7.5-GHZ GAAS-MESFET MACROCELL ARRAY

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1989年第5期24卷 1265-1270页

作者： INO, M TOGASHI, M HORIGUCHI, S HIRAYAMA, M KATAOKA, H NIPPON TELEGRAPH & TEL PUBL CORP MUSASHINO ELECT COMMUN LAB COMMUN SWITCHING LABS MUSASHINO TOKYO 180 JAPAN

An ECL-compatible GaAs 250-gate macrocell array has been successfully designed and fabricated using a three-level series gate low-power source-coupled FET logic (LSCFL) and a newly developed 0.4- mu m-gate self-aligned MESFET process. The unloaded propagation delay time was 30 ps/gate at a 2.4-mW/gate power dissipation. The loaded delay time with fan-out=3 and a 2-mm line length was as fast as 74 ps. The flip-flop toggle frequency was 7.5 GHz. A 2*2 asynchronous transfer mode (ATM) switch circuit was constructed on the macrocell array, and a maximum operation frequency of 2 GHz was achieved.< >

关键词： Gallium arsenide MESFETs Macrocell networks logic arrays Frequency Asynchronous transfer mode Switches FETs logic design Propagation delay

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A 30-NS CYCLE TIME 4-MB MASK ROM

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1994年第11期29卷 1353-1358页

作者： SUNAGA, T Yasu Technology Application Laboratory IBM Japan Limited Japan

A 4-Mb mask ROM in a 256-Kb x 16 organization is described. It is fabricated with a 1.0-mu m CMOS process, using single polysilicon, two levels of metal, and 3.0 x 4.4 mu m(2) X-cells. Unlike conventional ROM's, it implements a DRAM type RAS/CAS control scheme. A RAS access time of 60 ns is measured. For a fast data access, the chip has a consecutive address read mode in which the system needs to supply only a first address and subsequent addresses are generated in the ROM chip at every CAS clock. A 30-ns cycle time is demonstrated in this mode. 16-b data pins are also used for RAS/CAS multiplexed address inputs. Because of this three way pin multiplexing, the 7.5 x 10.5 mm(2) chip needs only 28 pins for its 400-mil SOJ package.

关键词： Read only memory Pins Packaging Clocks CMOS technology CMOS process Semiconductor device measurement Content addressable storage logic arrays Random access memory

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A KNOWLEDGE-BASED TEST GENERATOR FOR STANDARD CELL AND ITERATIVE ARRAY logic-CIRCUITS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1988年第2期23卷 428-436页

作者： VARMA, P TOHMA, Y TOKYO INST TECHNOL DEPT COMP SCIMEGURO KUTOKYO 152JAPAN

The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.< >

关键词： Circuit testing logic testing logic arrays logic circuits Character generation Automatic testing Circuit faults Very large scale integration Automatic logic units

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