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检索条件"主题词=Logic arrays"

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9T SRAM Cell Based Wired-OR logic arrays for Tsetlin Machine Inference

9T SRAM Cell Based Wired-OR Logic Arrays for Tsetlin Machine...

引用

Tsetlin Machine (ISTM), International Symposium on the

作者： Komal Krishnamurthy Shengyu Duan Jesse Ojukwu Omar Ghazal Alex Yakovlev Rishad Shafik Microsystems Research Group Newcastle University UK University of Mosul Iraq

ISBN: (数字)9798331504984

ISBN: (纸本)9798331504991

Tsetlin Machine (TM) has recently emerged as a promising alternative to arithmetically driven machine learning algorithms, such as deep neural networks (DNNs). TMs are based on single-layered propositional logic followed by summative voting between conjunctive clauses. Although, the logic underpinning has been demonstrated with significantly lower complexity than DNNs, TM's memory footprint can grow dramatically when the model size increases. While designing hardware accelerator architecture, such an increase in the complexity can be associated with significantly increased data movement overheads. In this paper, we propose a processing in-memory (PIM) inspired TM inference architecture. Central to this architecture are 9-transistor (9T) static random access memory (SRAM) Wired-OR logic arrays, fitting the natural logic underpinning of TM. The implementation of Wired-OR logic using 9T SRAM cells provides the crucial embedding of logic with storage, thereby reducing the overall logic complexity and data movement costs significantly. Through extensive simulations, we analyze the functional properties of the inference accelerator. Further, we study scalability under multiple Tsetlin automata scenarios and investigate parametric behaviors such as power consumption, PVT variations and Monte Carlo simulations. We show that our design achieves 72 % area reduction per TA propositional logic when compared with a vanilla CMOS design implementing the TAs using flip-flops.

关键词： Microprocessors Simulation Noise Computer architecture SRAM cells Complexity theory logic Transistors Transient analysis logic arrays

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High-speed LSI current-mode-logic arrays for LIMAC

High-speed LSI current-mode-logic arrays for LIMAC

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： A. Rashid RCA Somerville NJ USA

Design and fabrication of high-speed 72- and 144- gate arrays developed for the LIMAC computer will be described. arrays employ a low-power current mode logic cell with 4 to 5-ns propagation delay at 10 mW to provide ... 详细信息

关键词： Large scale integration logic arrays Aerospace electronics Arithmetic Packaging Bonding Laboratories Contracts Resistors Voltage

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Testing iterative logic arrays for delay faults with a constant number of patterns

Testing iterative logic arrays for delay faults with a const...

引用

International Symposium on Electronic Materials and Packaging

作者： Shyue-Kung Lu Mau-Jung Lu Department of Electronic Engineering Fu Jen Catholic University Taipei Taiwan

ISBN: (纸本)078037682X

Iterative logic arrays (ILAs) are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. In order to ascertain the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as sequential fault models and delay fault models should also be targeted. A cell delay fault occurs if and only if an input transition cannot be propagated to the cell's output through a path in the cell in a specified clock period. It has been shown that all SIC (single input change) pairs of a circuit are sufficient to detect all robustly detectable path delay faults within the circuit. We extend the concept of SIC pairs for iterative logic arrays. We say that an ILA is C-testable for cell delay faults if it is possible to apply all SIC (single input change) pairs to every cell of the array in such a way that the number of test pairs for the array is a constant. Necessary conditions for sending this test set to each cell in the array and propagating faulty effects to the primary outputs are derived. An efficient algorithm is also presented to obtain such a test sequence. We use the pipelined array multiplier as an example to illustrate our approach. The number of test pairs for completely testing of the array is only 80. Moreover, the hardware overhead to make it delay fault testable is about 6%.

关键词： logic testing logic arrays Delay Circuit faults Silicon carbide Circuit testing Electrical fault detection Fault detection Digital signal processors Very large scale integration

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Power reduction in large fan-in CMOS gates in logic arrays using selective precharge

Power reduction in large fan-in CMOS gates in logic arrays u...

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Great Lakes Symposium on VLSI

作者： C.A. Zukowski S.-Y. Wang Department of Electrical Engineering Columbia University USA

A general technique to reduce the energy used by individual CMOS logic gates in large fan-in logic arrays is derived. A fairly small subset of the array inputs is used to do a partial calculation the results of which can be used to significantly reduce energy use in the rest of the array by avoiding unnecessary charge/discharge cycles. This can be done without significantly reducing the speed, leading to a vastly improved energy-delay product in certain applications such as a PLA and a comparator array. Estimates of the optimal location for the partition and the performance gain as a function of various parameters of the logic array are provided.

关键词： CMOS logic circuits logic arrays logic gates Switches Programmable logic arrays Decoding Computer aided manufacturing CADCAM Fault location Read only memory

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Area-efficient implication circuits for very dense Lukasiewicz logic arrays

Area-efficient implication circuits for very dense Lukasiewi...

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International Symposium on Multiple-Valued logic

作者： J.W. Mills Indiana University Bloomington IN USA

A one-diode circuit for negated implication is derived from a 12-transistor Lukasiewicz implication circuit. The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower LLA contains 36000 implications in an area that previously held 92 implications; the three-transistor LLA contains 1990 implications. Both LLAs double the number of inputs per pin on the IC package. Very dense LLAs make LLA-based architectures practical. As an example, an LLA retina that detects edges in 15 ns is described.< >

关键词： logic arrays logic circuits Schottky diodes Analog circuits Electronic circuits Analog computers Fuzzy logic Cost accounting Milling machines Electronics packaging

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Implementation of fault-tolerant sequential circuits using programmable logic arrays

Implementation of fault-tolerant sequential circuits using p...

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Great Lakes Symposium on VLSI

作者： N. Misra A.K. Goel Department of Electrical Engineering Michigan Technological University Houghton MI USA

An efficient implementation procedure has been developed for the realization of sequential circuits using PLAs. The synthesis procedure is simple and based on a heuristic approach. Synchronous sequential circuits which have been widely used in digital computers over the years can be easily implemented in a single chip layout. One of the major advantages of this method is the reduction in chip area in terms of the fusible links blown to realize the state machine using PLAs.< >

关键词： Programmable logic arrays Sequential circuits Fault tolerance Equations logic design Silicon Timing Clocks Hazards logic arrays

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A general BIST-amenable method of test generation for iterative logic arrays

A general BIST-amenable method of test generation for iterat...

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VLSI Test Symposium

作者： I.O. Boateng H. Takahashi Y. Takamatsu Department of Computer Science Ehime University Japan

In this work, we call a set of a constant number of test patterns that have a fixed fault coverage for any size of a given ILA a fixed coverage fixed size test set (FixCoST). In this paper, we first show the existence of FixCoSTs, each test pattern of which is applied to the rows and columns of the array under test, as binary patterns that are repetitions of a few cell-input patterns. Such FixCoSTs can be applied in a BIST framework. Next, we devise a means and formulate measures to evaluate the individual repetitive test patterns of such a FixCoST and the FixCoST as a set. Then, we exploit the repetitive nature of the constituent test patterns of the FixCoSTs to develop a BIST-amenable method for generating FixCoSTs that apply all permutations of binary patterns to each cell of the ILA under test.

关键词： logic testing logic arrays Iterative methods

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Simulated annealing for folding of programmable logic arrays

Simulated annealing for folding of programmable logic arrays

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IEE Colloquium on Synthesis and Optimisation of logic Systems

作者： J.M. Sanchez J. Ballesteros Dept. de Inf. y Autom. Univ. Complutense Madrid Spain

Addresses the multiple column folding using a methodology using the SA algorithm. First of all, the multiple unconstrained column folding is studied. Then the SA algorithm for solving several constrained folding probl... 详细信息

关键词： logic arrays logic design Simulated annealing Very-large-scale integration

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CMOS VLSI Lukasiewicz logic arrays

CMOS VLSI Lukasiewicz logic arrays

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International Conference on Application Specific Array Processors

作者： J.W. Mills C.A. Daffinger Department of Computer Science Indiana University Bloomington IN USA Dept. of Comput. Sci. Indiana Univ. Bloomington IN USA

Lukasiewicz logic arrays (LLAs) are massively parallel analog computers organized as binary trees of identical processing elements. The authors have designed and performed preliminary tests on a series of CMOS VLSI LLAs whose cells perform Lukasiewicz implication ( to ). The authors describe the LLA architecture and its relationship to cellular automata, describe the CMOS VLSI implementation of versions LL9 and LL10 and their initial characterization, and report on the results obtained by programming LL9 and LL10 as fuzzy function recognizers, the first step in designing more general function units such as expert systems and neural networks. Initial test results showed that the LLAs implemented the notch function linearly, but with a slope that varied from that of the ideal function. Trimming the LLA inputs and outputs is expected to result in a typical error of less than 2%, and a mean error of less than 0.5%.< >

关键词： logic arrays Very large scale integration CMOS logic circuits Performance evaluation Testing Analog computers Binary trees Computer architecture Automatic programming Functional programming

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Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays

Synthesis of reversible circuits for testing with universal ...

引用

International Conference on VLSI Design

作者： A. Chakraborty IBM-Global Services India

Reversibility is of interest in the design of very low-power circuits; it is essential for quantum computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT) gates. Most commonly used stuck-at fault model (both single stuck-at fault (i.e. SSF) and multiple stuck-at fault (i.e. MSF)) has been assumed to be type of fault for such circuits. We define a universal test set (UTS) for a family C(n) of n-input circuits with respect to fault model F as a family of test sets T/sub UTS/ such that each C(n) has a unique test set T(n) in T/sub UTS/ that detects all F-type faults in every member of C(n). We show that if k /spl ges/ 2 for all gates, then the n-wire reversible circuits have a UTS of size n with respect to MSFs. By synthesizing 0-CNOT (inverters) and 1-CNOT gates from 2-CNOT (Toffoli) gates this result can be extended to all circuits of interest. We also present a method for modifying an n-wire reversible circuit to reduce its UTS size to 3. By modeling a k-CNOT gate as a k-input AND gate and a 2-input EXOR gate we then examine testability for the SSF model. Noting their resemblance to classical (irreversible) Reed-Muller circuits, which are well known to be easily testable, we prove that the n-wire reversible circuits have a UTS of size n/sup 2/ + 2n + 2. Finally, we turn to the reversible counterparts of another easily-testable classical circuit family, iterative logic arrays (ILAs). We define d-dimensional reversible ILAs (RILAs) and prove that they require a constant number test vectors irrespective of array length under the single cell fault (i.e. SCF) model; this number is determined by the size of the RILA cell's state table.

关键词： Circuit testing logic testing logic arrays Circuit synthesis logic circuits Circuit faults Quantum computing Electrical fault detection Fault detection Inverters

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