Using a magnetoelectric spin-orbit circuit, this study suggests a revolutionary method for developing scale and cost-effective computer. Despite semiconductors miniaturization, the leading technology of today, CMOS, h...
详细信息
The active participation of external entities in the manufacturing flow has produced numerous hardware security issues in which piracy and overproduction are likely to be the most ubiquitous and expensive ones. The ma...
详细信息
ISBN:
(纸本)9783981926347
The active participation of external entities in the manufacturing flow has produced numerous hardware security issues in which piracy and overproduction are likely to be the most ubiquitous and expensive ones. The main approach to prevent unauthorized products from functioning is logic encryption that inserts key-controlled gates to the original circuit in a way that the valid behavior of the circuit only happens when the correct key is applied. The challenge for the security designer is to ensure neither the correct key nor the original circuit can be revealed by different analyses of the encrypted circuit. However, in state-of-the-art logic encryption works, a lot of performance is sold to guarantee security against powerful logic and structural attacks. This contradicts the primary reason of logic encryption that is to protect a precious design from being pirated and overproduced. In this paper, we propose a bilateral logic encryption platform that maintains high degree of security with small circuit modification. The robustness against exact and approximate attacks is also demonstrated.
The high performance computing architectures are the primary need for the modern devices having compute-intensive applications such as signal and image processing. This paper presents a novel low complexity carry-skip...
详细信息
ISBN:
(纸本)9781728146553
The high performance computing architectures are the primary need for the modern devices having compute-intensive applications such as signal and image processing. This paper presents a novel low complexity carry-skip adder design that provides high-speed and consumes low-power making it suitable for the development of high-performance signal processing cores. The proposed adder is derived from the reformulated Boolean expressions that avoid the redundant computations with reduced critical path delay. The proposed architectures are coded in VHDL and synthesized with Synopsys Design Compiler using 65nm CMOS library. Synthesis results demonstrate that the proposed 32-bit carry skip adder reduces the delay, area and power by 10.2%, 13.6% and 8% respectively than the best known carry skip adder. Finally, the proposed 16- and 32-bit adders reduce the area-delay product by 14.4% and 22.5% respectively over the existing adder.
The active participation of external entities in the manufacturing flow has produced numerous hardware security issues in which piracy and overproduction are likely to be the most ubiquitous and expensive ones. The ma...
详细信息
ISBN:
(纸本)9783981926347
The active participation of external entities in the manufacturing flow has produced numerous hardware security issues in which piracy and overproduction are likely to be the most ubiquitous and expensive ones. The main approach to prevent unauthorized products from functioning is logic encryption that inserts key-controlled gates to the original circuit in a way that the valid behavior of the circuit only happens when the correct key is applied. The challenge for the security designer is to ensure neither the correct key nor the original circuit can be revealed by different analyses of the encrypted circuit. However, in state-of-the-art logic encryption works, a lot of performance is sold to guarantee security against powerful logic and structural attacks. This contradicts the primary reason of logic encryption that is to protect a precious design from being pirated and overproduced. In this paper, we propose a bilateral logic encryption platform that maintains high degree of security with small circuit modification. The robustness against exact and approximate attacks is also demonstrated.
Linear authorization logics (LALs) are logics based on linear logic that can be used for modeling effect-based authentication policies. LALs have been used in the context of the Proof-Carrying Authorization framework,...
详细信息
Linear authorization logics (LALs) are logics based on linear logic that can be used for modeling effect-based authentication policies. LALs have been used in the context of the Proof-Carrying Authorization framework, where formal proofs must be constructed in order for a principal to gain access to some resource elsewhere. This paper investigates the complexity of the provability problem, that is, determining whether a formula is provable in a linear authorization logic. We show that the multiplicative propositional fragment of LAL is already undecidable in the presence of two principals. On the other hand, we also identify a first-order fragment of LAL for which provability is PSPACE-complete. Finally, we argue by example that the latter fragment is natural and can be used in practice. (C) 2014 Elsevier B.V. All rights reserved.
An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum numbe...
详细信息
An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p - 1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.
The logic complexity and computational complexity of decoders for BCH codes are investigated, and bounds on complexity are obtained. These are compared with earlier. results of Savage for arbitrary block codes and for...
详细信息
The logic complexity and computational complexity of decoders for BCH codes are investigated, and bounds on complexity are obtained. These are compared with earlier. results of Savage for arbitrary block codes and for some special decoding rules. It is found that decoders for the class of BCH codes are of much lower complexity.
暂无评论