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Delhi Section Conference (DELCON), IEEE

作者： Nikita Mahoviya Prabhat Singh Dharmendra Singh Yadav Electronics and Communication Engineering Department National Institute of Technology Hamirpur India

For digital applications, researchers are looking into tunnel field-effect transistors (TFETs) as a possible substitute for MOSFETs. TFETs offer several unique qualities that can be used in digital applications. Utilizing two-dimensional device simulations, a single DGTFET is presented in this paper to implement various logic functions. It is demonstrated that by biasing the two gates individually, DGTFET can be used to implement logic operations like OR and AND. Using the overlap of gate-source region (Lov) and opting the optimum silicon wafer thickness are crucial to getting distinct logic functions from a DGTFET. These applications show that it is possible to compactly create logic functions by taking advantage of the special TFET characteristics namely, ambipolar nature and tunneling’s dependence on gate controlling capability over channel region.

关键词： Semiconductor device modeling Plasma properties MOSFET TFETs IEEE Sections logic gates logic functions

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One instruction set computer with optimised polarity-tunable model of double gate CNTFETs

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IET CIRCUITS DEVICES & SYSTEMS 2020年第6期14卷 770-779页

作者： Ponnayan, Reena Monica Thazhathu, Sreedevi Vellithiruthi Vellore Inst Technol Sch Elect Engn Chennai Tamil Nadu India

Emerging devices such as double gate carbon nanotube field effect transistors (DG CNTFETs) have opened up manifold possibilities for reconfigurable logic design. The thickness of gate oxide and the employment of inhomogeneous dielectrics over and under the carbon nanotubes (CNTs) impact the operation of DG CNTFETs. In this work, the dielectric constant and the thickness of the gate oxide are optimised to suppress the ambipolar conduction in CNTFETs. A multi-objective genetic algorithm-based approach is proposed to optimise these parameters. The contributions in this study are two-fold: firstly, a DG CNTFET is fabricated with the optimised parameters. By exploiting the ability to select the conduction behaviour using a second gate in the fabricated DG CNTFETs, the device is electrostatically programmed to behave as an n or p-type CNTFET. Secondly, a one instruction set computer is simulated with the optimised model of DG CNTFET. A universal static logic cell which implements 16 logic functions, a D-Latch and a D-FF were built with DG CNTFETs. The logic circuits with polarity-tunable DG CNTFETs outperform other logic structures. There is a 40% betterment in performance primarily due to the reduced number of logic levels and by 25% due to the reduced delay.

关键词： genetic algorithms logic circuits carbon nanotube field effect transistors permittivity semiconductor device models flip-flops one instruction set computer optimised polarity-tunable model double gate carbon nanotube field effect transistors gate oxide p-type CNTFET polarity-tunable DG CNTFET fabricated DG CNTFET double gate CNTFET reconfigurable logic design inhomogeneous dielectrics dielectric constant ambipolar conduction multiobjective genetic algorithm universal static logic cell logic circuits logic functions D-latch D-flip flops C

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Design of an Energy-Efficient Parity Function Circuit

Design of an Energy-Efficient Parity Function Circuit

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International Conference on Engineering and Emerging Technologies (ICEET)

作者： Jeong Beom Kim Dept. of Electronics Engineering Kangwon National University Chuncheon Republic of Korea

ISBN: (数字)9798350316926

ISBN: (纸本)9798350316933

In this paper, we introduce an energy-efficient parity function circuit that is implemented using XOR (exclusive-OR) and XNOR (exclusive-NOR) circuits. The proposed circuit reduces the internal load capacitance on the critical path and is designed with only 8 transistors. The circuit produces perfect output signals for all input combinations. The proposed parity function circuit demonstrates a 6.4 % reduction in average propagation delay time, a 29.7 % decrease in power dissipation, a 36.6% decrease in power-delay product (PDP), a 43.0% decrease in energy-delay product (EDP), and a 55.6% decrease in energy-delay-delay product (EDDP), respectively. Compared with the previous circuits, the proposed circuit exhibits the improved characteristics in terms of average propagation delay time, power dissipation, PDP, EDP, and EEDP. The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit performs the expected logic functions and achieves a reasonable performance.

关键词： Computer simulation Capacitance SPICE logic functions Energy efficiency Stability analysis Power dissipation

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Detection of negative sequence components in diagnosing and tolerating open-gate fault for a voltage-source inverter in an induction motor drive

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IET POWER ELECTRONICS 2020年第18期13卷 4194-4203页

作者： Al-Gahtani, Saad F. Azazi, Haitham Z. Nelms, Robert M. Elbarbary, Zakaria M. King Khalid Univ Coll Engn Elect Engn Dept Abha Saudi Arabia Menoufia Univ Fac Engn Elect Engn Dept Shibin Al Kawm Egypt Auburn Univ Elect & Comp Engn Dept Auburn AL 36849 USA Kafrelsheikh Univ Dept Elect Engn Fac Engn Kafr Al Sheikh Egypt

Power converter faults represent about 12% of electrical system faults. More than 31% of these converter faults are caused by the transistors in the converters. These transistor failures are classified into open-gate and short-gate faults. A fault diagnostic and tolerant control system is proposed in this study for an open-gate fault of a three-phase voltage-source inverter (VSI). The system under study is an induction motor fed by a VSI. The diagnostic technique uses a detection method of positive and negative sequence components, which requires only the measurement of motor currents. The diagnostic signals are derived from the negative sequence components of the motor currents. These signals are then compared using logic functions to trigger the tolerant control. In the case of an open-gate fault, the tolerant system converts the inverter topology from six switches to four switches where the faulty inverter leg is disconnected. The proposed control method was evaluated under steady-state and transient conditions through simulation and experiments. The results confirm an effective and reliable performance of the motor under an open-gate fault.

关键词： induction motor drives invertors fault diagnosis voltage-source convertors failure analysis transistors electric current measurement machine control power converter faults electrical system faults short-gate faults fault diagnostic tolerant control system three-phase voltage-source inverter negative sequence components motor currents tolerating open-gate fault induction motor drive transistor failures diagnostic technique detection method logic functions inverter topology faulty inverter steady-state conditions transient conditions

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Bi2O2Se-Perovskite Heterostructure Based Bipolar Photosensors as Reconfigurable logic-In-Sensor Devices

Bi2O2Se-Perovskite Heterostructure Based Bipolar Photosensor...

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IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

作者： Lei Xu Shuo Liu Ru Huang Ming He School of Integrated Circuits Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China Frontiers Science Center for Nano-optoelectronics Peking University Beijing China

Herein, we reported reconfigurable in-sensor logic gates based on $\text{Bi}_{2}\mathrm{O}_{2}\text{Se}$ -perovskite heterostructures. Notably, the photoresponsivity achieved the order of $10^{5}$ A/W with the specific detectivity of $10^{13}$ Jones. Tunable bipolar photoresponses were successfully adopted to demonstrate reconfigurable Boolean logic functions of “AND”, “OR”, “NAND”, and “NOR” within the photosensors, offering a promising route to manufacture novel logic-in-sensor devices.

关键词： Performance evaluation logic gates logic functions Manufacturing

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Blending Inverted Lectures and Laboratory Experiments to Improve Learning in an Introductory Course in Digital Systems

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IEEE TRANSACTIONS ON EDUCATION 2020年第3期63卷 144-154页

作者： Alcaraz, Raul Martinez-Rodrigo, Arturo Zangroniz, Roberto Rieta, Jose Joaquin Univ Castilla La Mancha Dept Elect Elect Automat Control & Commun Cuenca 16071 Spain Univ Castilla La Mancha Dept Comp Syst Cuenca 16071 Spain Univ Politecn Valencia Elect Engn Dept BioMIT Org Valencia 46022 Spain

Contribution: An improved inverted lecturing (IIL) framework based on blending flipped lectures and hands-on experiments provides instructional benefits, compared to traditional teaching (TT) and inverted lecturing (IL), in an introductory course in digital systems. Background: IL has proven more effective than TT in improving student learning in engineering courses, but has mostly been used for theory sessions. The impact of combining inverted lectures and hands-on experiments on student learning has not still been thoroughly assessed in engineering courses. Intended Outcomes: Attendance, marks, and satisfaction should improve for students in IL-based theory lectures, compared with those receiving TT, and should improve still further for students receiving the IIL-based method. Workload both for student and instructor should not increase significantly. Application Design: The three methods were compared in six consecutive offerings of the course. In the first two, TT was used for both theory and laboratory classes;in the next two, IL was used for theory lectures;and in the final two offerings the IIL-based scheme was used. The instructor, intended learning outcomes (ILOs), course syllabus, and student grading scheme were constant over the six semesters. A total of 184 students with similar backgrounds participated. Findings: Students under the IL- and IIL-based frameworks were more engaged than those receiving TT, and were more satisfied with their learning process. The IIL-based learners achieved the deepest conceptual understanding. Finally, the IL- and IIL-based methods did not significantly increase workload for either the students or the instructor.

关键词： Digital systems Education logic gates Digital circuits logic functions Communications technology Europe Active learning digital systems engagement flipped classroom laboratory student perception

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logic Synthesis of Approximate Circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第10期39卷 2503-2515页

作者： Venkataramani, Swagath Kozhikkottu, Vivek J. Sabne, Amit Roy, Kaushik Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

The ability of several important application domains to tolerate inexactness or approximations in a large fraction of their computations has lead to the advent of approximate computing, a new design paradigm that exploits the intrinsic error-resilient nature to optimize computing platforms for energy and performance. A promising approach to approximate computing is to design approximate circuits, or circuit implementations that are highly efficient but differ in functionality from their original specifications subject to a prespecified quality constraint. While a slew of manual design techniques for approximate circuits have demonstrated their significant potential, a key requirement for their mainstream adoption is to develop automatic methodologies and tools that are general and scalable to any given circuit and quality specification. In this article, we propose SALSA, a systematic methodology for automatic logic synthesis of approximate circuits. Given a golden RTL specification of a circuit and a quality constraint that defines the amount of error that may be introduced in the implementation, SALSA synthesizes an approximate version of the circuit that adheres to the prespecified quality bounds. We make two key contributions: 1) the rigorous formulation of the problem of approximate logic synthesis (ALS), enabling the generation of circuits that is corrected by construction and 2) mapping the problem of approximate synthesis into an equivalent traditional logic synthesis problem, thereby allowing the capabilities of existing synthesis tools to be fully utilized for ALS. In order to achieve these benefits, SALSA forms a virtual quality constraint circuit (QCC) that encodes the quality constraints using logic functions called Q-functions. It then captures the flexibility that engendered by them as approximation don't cares (ADCs), which are used for circuit simplification using traditional don't care-based optimization techniques. We utilized SALSA to automaticall

关键词： Tools Measurement Optimization Approximate computing logic functions Automation Systematics Approximate circuits approximate computing error resilience logic synthesis low power design

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Extending Boolean Methods for Scalable logic Synthesis

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IEEE ACCESS 2020年 8卷 226828-226844页

作者： Testa, Eleonora Amaru, Luca Soeken, Mathias Mishchenko, Alan Vuillod, Patrick Gaillardon, Pierre-Emmanuel De Micheli, Giovanni Swiss Fed Inst Technol Lausanne LSI CH-1015 Lausanne Switzerland Synopsys Inc Design Grp Sunnyvale CA 94085 USA Univ Calif Berkeley Dept Elect Engn & Comp Sci SECS Berkeley CA 94720 USA Synopsys F-38330 Grenoble France Univ Utah LNIS Salt Lake City UT 84112 USA

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties of a logic circuit (e.g., don't cares), but usually result in better optimization. In particular, Boolean resubstitution is considered one of the most powerful Boolean methods in logic synthesis. In this paper, we present three novel Boolean resubstitution algorithms designed to be scalable and runtime-effective in a modern synthesis flow. They make use of circuit partitioning techniques and Boolean filtering to be fast and computationally tractable. We also discuss different data structures and reasoning engines, namely truth tables, binary decision diagrams, and satisfiability, that are required to gather don't cares and functional information. As the choice of the engine determines the scalability of Boolean resubstitution we present different scenarios in which the Boolean methods are best driven by one or the other of these. We have implemented the presented resubstitution techniques together with state-of-the-art methods in an industrial logic optimization engine to create a novel resynthesis flow. Our global resynthesis flow achieves significant synthesis results: Within the EPFL synthesis competition, we improve the best-known area results when mapped into LUT-6;when embedded in a commercial EDA flow, the new Boolean resynthesis flow results in 3.12% combinational area savings and 1.34% WNS reduction after physical implementation, at contained (w.r.t. the time of the entire flow) runtime cost.

关键词： Engines Optimization Cognition Scalability Runtime Data structures logic functions logic synthesis Boolean optimization Boolean resubstitution area optimization

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A Novel XOR/XNOR Structure for Modular Design of QCA Circuits

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2020年第12期67卷 3327-3331页

作者： Wang, Lei Xie, Guangjun Hefei Univ Technol Sch Elect Sci & Appl Phys Hefei 230009 Peoples R China

Quantum dot cellular automata (QCA) is considered one of the most promising technologies to replace the current CMOS technology. Compared with the traditional transistor technology, the computation relies on a new paradigm based on the interaction between nearby QCA cells. It has significant advantages, such as operating frequency (THz), high device density, and low power consumption. In this brief, a novel XOR/XNOR-function logic gate with two inputs, two enable inputs and one output is proposed and designed in Quantum-dot Cellular Automata (QCA) nanotechnology. In order to demonstrate the functionality and capabilities of the proposed QCA-based XOR/XNOR architecture, performance is evaluated and analyzed. The proposed XOR/XNOR logic gate has a superb performance in terms of area, complexity, power consumption and cost function in comparison to some existing QCA-based XOR architectures. Moreover, some efficient circuits based on the proposed XOR/XNOR gate are designed in QCA.

关键词： logic gates Inverters Clocks Layout Electrostatics logic functions Simulation Circuit design nanoelectronics quantum-dot cellular automata XOR XNOR gate

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SIMPLER MAGIC: Synthesis and Mapping of In-Memory logic Executed in a Single Row to Improve Throughput

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第10期39卷 2434-2447页

作者： Ben-Hur, Rotem Ronen, Ronny Haj-Ali, Ameer Bhattacharjee, Debjyoti Eliahu, Adi Peled, Natan Kvatinsky, Shahar Technion Israel Inst Technol Andrew & Erna Viterbi Fac Elect Engn IL-32000 Haifa Israel Univ Calif Berkeley Fac Elect Engn & Comp Sci Berkeley CA 94720 USA Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore

In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore, a highly motivated objective in modern computer architecture. This article presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed synthesis and in-memory mapping of logic execution in a single row (SIMPLER), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic memristor-aided logic (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory single instruction, multiple data (SIMD) operations. Compared to the previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of 435x. When the previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least 5x, with 23x improvement in area and 20x improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency.

关键词： logic gates Throughput Memristors Tools logic functions Arrays logic design logic synthesis memristor-aided logic (MAGIC) memristive systems memristor memristive memory-processing unit (mMPU) throughput von Neumann architecture

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