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检索条件"主题词=Logic functions"

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Induction with Recursive Definitions in Superposition

Induction with Recursive Definitions in Superposition

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Formal Methods in Computer Aided Design (FMCAD)

作者： Márton Hajdu Petra Hozzová Laura Kovács Andrei Voronkov TU Wien University of Manchester and EasyChair

ISBN: (纸本)9781665402941

Functional programs over inductively defined data types, such as lists, binary trees and naturals, can naturally be defined using recursive equations over recursive functions. In first-order logic, function definitions can be considered as universally quantified equalities. Verifying functional program properties therefore requires inductive reasoning with both theories and quantifiers. In this paper we propose new extensions and generalizations to automate induction with recursive functions in saturation-based first-order theorem proving, using the superposition calculus. Instead of using function definitions as first-order axioms, we introduced new simplification rules for treating function definitions as rewrite rules. We guide inductive reasoning and strengthen induction schema using recursively defined functions. Our experimental results show that handling recursive definitions in superposition reasoning significantly improves automated reasoning with induction.

关键词： Design automation Superposition calculus Binary trees logic functions Cognition

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Design of Double-Masking Current-Mode CMOS Circuit Against Power Analysis Attacks

Design of Double-Masking Current-Mode CMOS Circuit Against P...

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International Conference on Electronic Measurement and Instruments, ICEMI

作者： Maoqun Yao Conghui Li Ziwei Xue School of Information Science and Technology Hangzhou Normal University Hangzhou China

ISBN: (纸本)9781665444927

In order to enhance the ability of current-mode CMOS circuits to resist power analysis attacks, we introduce dual-masking logic to form dual-masking current-mode CMOS logic (DM-CML). There are 4 possibilities for the mask value, which is random and unpredictable. When the attacker cannot obtain the accurate mask value, the actual calculation result of the circuit cannot be accurately obtained by attackers. The less correlation between data and power consumption enhances circuit ability to resist power analysis attacks. Through the simulation experiment of Hspice, the results show that the DM-CML has the correct logic function and constant power consumption, which enhances its ability to resist power attacks.

关键词： Semiconductor device modeling Power demand Correlation Instruments Resists logic functions CMOS technology

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Learning Boolean Circuits from Examples for Approximate logic Synthesis

Learning Boolean Circuits from Examples for Approximate Logi...

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Asia and South Pacific Design Automation Conference

作者： Sina Boroumand Christos-Savvas Bouganis George A. Constantinides Imperial College London London UK

ISBN: (数字)9781450379991

ISBN: (纸本)9781728180571

Many computing applications are inherently error resilient. Thus, it is possible to decrease computing accuracy to achieve greater efficiency in area, performance, and/or energy consumption. In recent years, a slew of automatic techniques for approximate computing has been proposed; however, most of these techniques require full knowledge of an exact, or ‘golden’ circuit description. In contrast, there has been significant recent interest in synthesizing computation from examples, a form of supervised learning. In this paper, we explore the relationship between supervised learning of Boolean circuits and existing work on synthesizing incompletely-specified functions. We show that when considered through a machine learning lens, the latter work provides a good training accuracy but poor test accuracy. We contrast this with prior work from the 1990s which uses mutual information to steer the search process, aiming for good generalization. By combining this early work with a recent approach to learning logic functions, we are able to achieve a scalable and efficient machine learning approach for Boolean circuits in terms of area/delay/test-error trade-off.

关键词： Training Energy consumption Supervised learning Machine learning logic functions Mutual information Lenses

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On Defect Tolerance of Nanocrossbar Arrays using Divide and Conquer Technique

On Defect Tolerance of Nanocrossbar Arrays using Divide and ...

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International Symposium on Devices, Circuits and Systems (ISDCS)

作者： Tanmoy Chaku Aarjesh Rakshit Ismail Sarkar Malay Kule Jalpaiguri Government Engineering College West Bengal India Heritage Institute of Technology Kolkata Indian Institute of Engineering Science and Technology Shibpur India

ISBN: (数字)9781665414784

ISBN: (纸本)9781665447508

The nanoscale designs usually face much higher defect rates as compared to the VLSI designs based on conventional lithography. New defect tolerant schemes are in required to achieve high yield at this scale. The crossbar-based architecture is one of the most promising nanoscale computational architectures. To understand various logic circuits using nanoscale crossbar arrays; these nano-crossbars containing crosspoints with defects can be utilised to map different logic functions. In this work, we use a novel technique for mapping different logic functions to respective rows of nano-crossbar arrays having defective crosspoints. The method proposed by us is to tolerate defects and make wise use of defective crossbar using divide and conquer technique. The experimental results show satisfactory performance of the proposed algorithm. Moreover, the proposed algorithm outperforms some earlier bio-inspired based mapping algorithms in terms of function mapping success percentage with the variation of defect percentage.

关键词： Performance evaluation Lithography Computer architecture Very large scale integration logic functions Nanoscale devices logic arrays

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Minimization of Switching Activity of Graphene Based Circuits

Minimization of Switching Activity of Graphene Based Circuit...

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International Conference on VLSI Design

作者： Subrata Das Petr Fiser Soumya Pandit Debesh Kumar Das Institute of Radio Physics & Electronics Calcutta University Kolkata India Faculty of Information Technology Czech Technical University in Prague Czech Republic Jadavpur University Kolkata India

Reduction of power dissipation is a key challenge of VLSI circuits designers. In traditional CMOS-based circuits, dynamic power dissipation occurs due to the switching activity, i.e., transitions at logic nodes. In graphene-based circuits, power dissipation is also caused by the switching activity. In this paper, we compute the switching activity of these circuits considering the switching at every transistor. We propose an algorithm to minimize the total switching activity of graphene-based logic circuits. The algorithm is tested on benchmark circuits and the results show the reduction of average switching activity, area, and switching activity × area respectively by 9.17%, 0.81 %, and 9.82%.

关键词： logic circuits Graphene Switches Very large scale integration logic gates Minimization logic functions

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A Novel design of Nano scale TIEO based single layer full adder and full subractor in QCA paradigm

A Novel design of Nano scale TIEO based single layer full ad...

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International Conference on ent Computing and Control Systems (ICICCS)

作者： K. Kalpana B. Paulchamy S. Chinnapparaj K. Mahendrakan A. AbdulHayum Hindusthan Institute of Technology Coimbatore India

CMOS design dimension strongly decreased by reducing of transistor volume. CMOS transistor shall not be very much compressed and then their current size because combination results in actual bounds are abrupt transmit impact, Impurity difference, raise rate of fabrication process and temperature during process are the added important factors that cause, today MOS technology comes to an end. As per record quantum dot cellular automata technology provides a bright future resource which provides a precise shortly of approaching technic. Enormous capacity technic (QCA) is to make it CMOS due its bettered characteristics like energy smart, huge density and prompt execution. Addition and subtraction is important part of primary operations in ALU. Full adder and subractor is a basic element to design multiplier and divider circuit. A new plan for full adder and full subractor by three inputs EXOR gate logic towards single layer through minimum count of QCA cells is submitted. The proposed structures is stimulated in QCA designer tool and their power analysis done in QCA designer E tool.

关键词： Temperature Power measurement Quantum dots logic gates Tools CMOS technology logic functions

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Memristive Combinational and Sequential logic for In-Memory Computing

Memristive Combinational and Sequential Logic for In-Memory ...

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IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

作者： Xiaodi Huang Ling Yang Yi Li Xiangshui Miao Wuhan National Laboratory for Optoelectronics School of Optical and Electronic Information Huazhong University of Science and Technology Wuhan China

In this work, memristive combinational logic and sequential logic are designed and experimentally demonstrated with low hardware and latency overheads. By utilizing four logic variables: the two terminal voltages, the resistance state of the bipolar memristors, and a direction variable, the implementation of memristive combinational and sequential logic functions can share the same circuit structure and operation method. Our study provides a feasible approach towards a memristive processor for unconventional in-memory computing.

关键词： Resistance Latches Memristors logic functions Hardware Manufacturing

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A Novel Decoder Design for logic Computation in SRAM: CiM-SRAM

A Novel Decoder Design for Logic Computation in SRAM: CiM-SR...

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IEEE India Conference (INDICON)

作者： Kanika Monga Sahil Aggarwal Nitin Chaturvedi S Gurunarayanan Birla Institute of Technology and Science Pilani Campus Pilani Rajasthan India

ISBN: (纸本)9781665441766

Computing-in-Memory is an emerging paradigm that promises to accelerate data-intensive computation by eliminating the back and forth data movement between the memory and processor. SRAM is an ideal candidate for implementing computation in memory as it offers benefits such as high speed, low power consumption, and high endurance. One of the most extensively explored techniques utilized to realize computation within the SRAM is reading out the voltage at the bitline, which corresponds to a valid logic function output. It also requires activation of multiple wordlines corresponding to the location of the stored operands in the memory. However, conventional address decoders in SRAM selects only one address at a time. Hence, addressing this challenge, we propose to design a novel decoder which support enabling of multiple wordline in a 6T bitcell based CiM-SRAM (Computing-in-Memory based SRAM) array for performing logic computation.

关键词： Power demand Conferences Memory management Pipelines Random access memory Voltage logic functions

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Design of Digital Data Selectors on FPGA in a Laboratory Environment

Design of Digital Data Selectors on FPGA in a Laboratory Env...

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International Scientific-Practical Conference Problems of Infocommunications Science and Technology

作者： Dmytro Havrilov Andrii Volovyk Leonid Koval Mikola Vasylkivskyi Andriy Semenov Natalia Havrilova Faculty of Infocommunications Radiolectronics and Nanosystems Vinnytsia National Technical University Vinnytsia Ukraine

ISBN: (纸本)9781665406833

In this paper introduced the basics of designing digital devices on the field-programmable gate array (FPGA). The article describes the process of creating a digital combinational device using the laboratory board Altera UP2. The design of the device on multiplexers and demultiplexers of various types was carried out. The article considers the use of mega-functions, as well as the basics of their creation for the implementation of a digital data processing and transmission system. It also shows the process of configuring megafunctions using the auto-create manager. In the computeraided design system Quartus II, the research and programming of the created device was carried out. This technique for creating digital data selectors based on various types of devices can be used for education in the laboratory and creating optimized devices of this type.

关键词： Multiplexing Laboratories Education logic gates logic functions Data processing Field programmable gate arrays

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Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures

Dynamical Decomposition and Mapping of MPMCT Gates to Neares...

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Asia and South Pacific Design Automation Conference

作者： Atsushi Matsuo Wakaki Hattori Shigeru Yamashita IBM Research Ritsumeikan University

ISBN: (数字)9781450379991

ISBN: (纸本)9781728180571

We usually use Mixed-Polarity Multiple-Control Toffoli (MPMCT) gates to realize large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that has some physical limitation; (1) we need to decompose MPMCT gates into one or two-qubit gates, and then (2) we need to insert SWAP gates such that all the gates can be performed on Nearest Neighbor Architectures (NNAs). Up to date, the above two processes have been independently studied intensively. This paper points out that we can decrease the total number of the gates in a circuit if the above two processes are considered dynamically as a single step; we propose a method to inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Our additional idea is to consider the effect on the latter part of a circuit carefully by considering the qubit layout when composing an MPMCT gate. We show some experimental results to confirm the effectiveness of our method.

关键词： Performance evaluation logic circuits Qubit Layout Computer architecture logic gates logic functions

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