检索结果-内蒙古大学图书馆

International Scientific Conference Electronics (ET)

作者： Adriana N. Borodzhieva Gyunay S. Basriev Department of Telecommunications Faculty of Electrical Engineering Electronics and Automation University of Ruse “Angel Kanchev” 8 Studentska Str. Ruse Bulgaria

ISBN: (数字)9798350376449

ISBN: (纸本)9798350376456

The paper examines different ways to implement a Boolean function of three variables-through Basis 1 logic gates, through four-input multiplexers, and through cascading of two-input multiplexers. Algorithms are proposed for the implementation of the function in the last two cases in the “unconventional solution”, which will be explained in detail in the paper. The implementation in Logisim of these two cases with integrated circuits of the $\mathbf{7 4 x x}$ series, manufactured by Texas Instruments, is demonstrated.

关键词： Multiplexing Integrated circuits Wiring logic gates logic functions Teamwork Circuit synthesis

来源：评论

学校读者我要写书评

暂无评论

Input Variable Bypass or IVB Technique for logic functions Simplification

Input Variable Bypass or IVB Technique for Logic Functions S...

引用

Devices for Integrated Circuit (DevIC)

作者： Heranmoy Maity Parna Kundu Aritra Bhowmik Arijit Kr Barik Chitkara Uhiversity Institute of Engineering and Technology Chitkara University Punjab India Dept. of ECE NSHM Knowledge Campus Durgapur India Department of ECE Dr. B. C. Roy Engineering College Durgapur India Dept. of ETC Ramkrishna Shilpamandira Belur Howrah India

In this article a novel simplification technique has been proposed. The input variable bypass technique or IVB technique is proposed for logic function simplification, which is used to minimize the logic functions very easily. If any output equation is simplified from the truth table and this output equation is the function of a few variables, then others output equations can be simplified from the previous output function. One can be neglect or bypass the used input variable for logic simplification.

关键词： Input variables Very large scale integration logic functions

来源：评论

学校读者我要写书评

暂无评论

Novel Methods for Efficient Realization of logic functions Using Switching Lattices

引用

IEEE TRANSACTIONS ON COMPUTERS 2020年第3期69卷 427-440页

作者： Aksoy, Levent Altun, Mustafa Istanbul Tech Univ Emerging Circuits & Computat ECC Grp Dept Elect & Commun Engn TR-34469 Istanbul Turkey

Two-dimensional switching lattices including four-terminal switches are introduced as alternative structures to realize logic functions, aiming to outperform the designs consisting of one-dimensional two-terminal switches. Exact and approximate algorithms have been proposed for the problem of finding a switching lattice which implements a given logic function and has the minimum size, i.e., a minimum number of switches. In this article, we present an approximate algorithm, called janus, that explores the search space in a dichotomic search manner. It iteratively checks if the target function can be realized using a given lattice candidate, which is formalized as a satisfiability (SAT) problem. As the lattice size and the number of literals and products in the given target function increase, the size of a SAT problem grows dramatically, increasing the run-time of a SAT solver. To handle the instances that janus cannot cope with, we introduce a divide and conquer method called medea. It partitions the target function into smaller sub-functions, finds the realizations of these sub-functions on switching lattices using janus, and explores alternative realizations of these sub-functions which may reduce the size of the final lattice. Moreover, we describe the realization of multiple functions in a single lattice. Experimental results show that janus can find better solutions than the existing approximate algorithms, even than the exact algorithm which cannot determine a minimum solution in a given time limit. On the other hand, medea can find better solutions on relatively large size instances using a little computational effort when compared to the previously proposed algorithms. Moreover, on instances that the existing methods cannot handle, medea can easily find a solution which is significantly better than the available solutions.

关键词： Lattices Switches Approximation algorithms logic gates logic functions Transistors CMOS technology Binary search emerging technologies four-terminal switch logic synthesis switching lattice satisfiability

来源：评论

学校读者我要写书评

暂无评论

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input logic functions

Standard Cell and Supergates Designs: An Electrical Comparis...

引用

IEEE International Symposium on Circuits and Systems

作者： Henrique Kessler Marcelo Porto Leomar Da Rosa Vinicius V. Camargo Posgrdue Progr in Couing - PPGC Feder Universiy of Peos - UFPe Peos BrziPosgrdue Progr in Couing - PPGC Feder Universiy of Peos - UFPe Peos BrziPosgrdue Progr in Couing - PPGC Feder Universiy of Peos - UFPe Peos BrziCener for Technoogic Deveoen - CDTec Feder Universiy of Peos - UFPe Peos Brzi

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

This paper presents an electrical study on logic functions with up to 4 inputs designed with a standard cell mapping and two automatically generated supergates methodologies. The results indicate that supergate-based designs reduce the average power in 84.4% of the studied cases while reducing area by 12.9%. Despite the supergate design increasing in average the circuit critical delay by 5.8%, it achieves better power-delay-product in 2823 (70.9%) of the 3982 studied logic functions. The reduction of logic levels is the main factor for gains obtained with supergates due to the glitch power reduction.

关键词： Measurement Design methodology logic gates Electric variables logic functions Delays Power dissipation

来源：评论

学校读者我要写书评

暂无评论

Lead-Free Perovskites-Based Photonic Synaptic Devices with logic functions

引用

ADVANCED MATERIALS TECHNOLOGIES 2021年第12期6卷

作者： Hao, Dandan Liu, Dapeng Zhang, Junyao Wang, Yan Huang, Jia Tongji Univ Sch Mat Sci & Engn Frontiers Sci Ctr Intelligent Autonomous Syst Interdisciplinary Mat Res Ctr Shanghai 201804 Peoples R China Tongji Univ Shanghai Peoples Hosp 4 Translat Res Inst Brain & Brain Intelligence Shanghai 200434 Peoples R China

Lead halide perovskites have shown great potential in photonic synaptic devices owing to their notable optical properties. However, the inherent toxicity of lead and complex configuration of the device hinder the further development of perovskites-based photonic synaptic devices. Here, lead-free double perovskite Cs2AgSbBr6 is first used to fabricate photonic synaptic devices. The photonic synaptic device with a simple structure exhibits decent reproducibility and stability. By tuning external light signals, photonic synaptic devices based on Cs2AgSbBr6 can mimic primary synaptic behaviors, such as excitatory postsynaptic current, paired pulse facilitation, short-term memory (STM), long-term memory (LTM), the transfer between STM and LTM, and the "learning-forgetting-relearning" process. Furthermore, the temperature effect on the learning and memory process is investigated. Importantly, logic functions of "OR" and "AND" operations are realized. This work suggests the great potential of Cs2AgSbBr6 in future neuromorphic computation.

关键词： lead-free double perovskites logic functions long-term memory photonic synaptic devices stability

来源：评论

学校读者我要写书评

暂无评论

A Novel Method for the Realization of Complex logic functions using Switching Lattices

A Novel Method for the Realization of Complex Logic Function...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Levent Aksoy Mustafa Altun Department of Electronics and Communication Engineering Istanbul Technical University 34469 Maslak Istanbul Turkey

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Over the years, efficient algorithms have been proposed to realize logic functions on two-dimensional arrays of four-terminal switches, called switching lattices, using the fewest number of switches. Although existing algorithms can easily find a solution on logic functions with a small number of inputs and products, they can hardly handle large size instances. In order to cope with such logic functions, in this paper, we introduce SISYPHUS that exploits Boolean decomposition techniques and incorporates a state-of-art algorithm designed for the realization of logic functions using switching lattices. Experimental results indicate that SISYPHUS can find competitive solutions on logic functions with a small number of inputs and products when compared to those of previously proposed algorithms. Moreover, its solutions on large size functions are obtained using a little computational effort and are significantly better than the best solutions found so far.

关键词： Lattices logic functions Switches Search problems Upper bound Complexity theory

来源：评论

学校读者我要写书评

暂无评论

Electroluminescent synaptic devices with logic functions

引用

NANO ENERGY 2018年 54卷 383-389页

作者： Zhao, Shuangyi Ni, Zhenyi Tan, Hua Wang, Yue Jin, Hao Nie, Tongxin Xu, Mingsheng Pi, Xiaodong Yang, Deren Zhejiang Univ State Key Lab Silicon Mat Hangzhou 310027 Zhejiang Peoples R China Zhejiang Univ Sch Mat Sci & Engn Hangzhou 310027 Zhejiang Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Zhejiang Peoples R China

The incorporation of light into synaptic devices for neuromorphic computing with low energy consumption and high intelligence is greatly inspired by the development of optogenetics in neuroscience. However, the use of light as the outputs of synaptic devices has not been demonstrated yet, impeding the full optoelectronic integration of artificial neural systems. Here we demonstrate electroluminescent synaptic devices based on silicon nanocrystals (Si NCs) with optical outputs. These devices exhibit a series of important synaptic functionalities including paired-pulse facilitation (PPF), transition from short-term plasticity (STP) to long-term plasticity (LTP) and spike-timing-dependent plasticity (STDP). In the meantime, logic functions such as "AND", "OR", "NAND" and "NOR" are realized in the intercoupled Si-NC-based electroluminescent synaptic devices. The current results not only help realize the bidirectional conversion between electrical and optical signals in synaptic devices, but also contribute to the development of the in-memory computing capacity of synaptic devices.

关键词： Electroluminescence Synaptic plasticity logic functions Neuromorphic computing

来源：评论

学校读者我要写书评

暂无评论

Architecture and Optimization of Associative Memories used for the Implementation of logic functions based on Nanoelectronic 1S1R Cells

Architecture and Optimization of Associative Memories used f...

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Heittmann, Arne Noll, Tobias G. Rhein Westfal TH Aachen Chair Integrated Digital Syst & Circuit Design Aachen Germany

ISBN: (纸本)9783981926309

A neuromorphic architecture based on Binary Associative memories and nanoelectronic resistive switches is proposed for the realization of arbitrary logic/arithmetic functions. Subsets of non-trivial code sets based on error detecting 2-out-of-n-codes are thoroughly used to encode operands, results, and intermediate states in order to enhance the circuit reliability by mitigating the impact of device variability. 2-ary functions can be implemented by cascading a mixer memory, a correlator memory, and a response memory. By introduction of a new cost function based on class-specific word line-coverage, stochastic optimization is applied with the aim to minimize the overall number of active amplifiers. For various exemplary functions optimized architectures are compared against solutions obtained using a standard-cost function. It is especially shown that the consideration of word-line-coverage results in a significant circuit compaction.

关键词： Resistive Switches Selector Device Associative Memory Clipped Hebbian Synaptic Rule Reliability logic functions arithmetic function nanoelectronics BiNAM

来源：评论

学校读者我要写书评

暂无评论

A New Approach For Constructing logic functions After ECO 25

A New Approach For Constructing Logic Functions After ECO

引用

25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Gharehbaghi, Amir Masoud Fujita, Masahiro Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan Univ Tokyo VLSI Design & Educ Ctr Tokyo Japan

ISBN: (纸本)9781538628805

Engineering change orders (ECO) are small changes in the design due to last minute bug fixes or spec changes. In this paper, we focus on functional ECO in a logic design and try to construct the new logic function, reusing the existing logic as much as possible. Traditional approaches try to find appropriate locations in the original design that their modifications may result in the new functionality. However, those methods usually fail if additional inputs are required. We propose a new approach based on iterative SAT solving to find the inputs of the function for the given internal nodes, or the primary outputs that are the target of the ECO, out of all the internal signals and primary inputs such that it is guaranteed to be able to correct the functionality without explicitly generating the functions. Our experimental results on ITC99 benchmarks show the efficiency and effectiveness of our approach, specially for hard ECO cases.

关键词： Table lookup Debugging Computer bugs Sequential circuits Multiplexing logic functions Electronic mail

来源：评论

学校读者我要写书评

暂无评论

A new approach for selecting inputs of logic functions during debug

A new approach for selecting inputs of logic functions durin...

引用

IEEE International Symposium on Quality Electronic Design

作者： Amir Masoud Gharehbaghi Masahiro Fujita Dept. of Electrical Engineering and Information Systems University of Tokyo Japan VLSI Design and Education Center (VDEC) The University of Tokyo Japan

ISBN: (纸本)9781509054053

Debugging logic functions involves finding the function of some of the internals nodes such that their functionality becomes correct, according to the given specification. In some cases, different new inputs are required for those internal nodes to be able to correct the functionality. In this paper, we propose an efficient method for selecting inputs of internal nodes during debug such that correction is guaranteed. Our method has a new different approach for debugging that focuses on finding the inputs of the functions without explicitly trying to find the new functions. This is done by iteratively solving SAT problems until we find the inputs. Our experimental results on ITC'99 benchmarks show the efficiency and effectiveness of our approach. The results show more than 30% reduction in the number of SAT problems to be solved as well as more than 85% reduction in debug time, on average, compared to the previous methods.

关键词： Debugging Table lookup Computer bugs Runtime Integrated circuit modeling logic functions Sequential circuits

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：