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Clocked Gate Reduction With Clockless Gates in Technology Mapping for RSFQ logic Circuits

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2025年第5期35卷

作者： Kito, Nobutaka Takagi, Kazuyoshi Takagi, Naofumi Chukyo Univ Sch Engn Toyota Aichi 4700393 Japan Mie Univ Grad Sch Engn Tsu Mie 5148507 Japan Kyoto Univ Grad Sch Informat Kyoto Japan Kanazawa Gakuin Univ Dept Informat Engn Ishikawa 9201392 Japan

Technology mapping is a process in logic synthesis for designing logic circuits. It converts an internal graph representation of logic functions into a gate-level netlist. This study proposes a method that involves introducing clockless gates proactively into resultant netlists of RSFQ logic circuits. Ordinary RSFQ circuits consist of clocked gates and necessitate path balancing. The usage of clockless gates working without clock inputs reduces the number of clocked gates and logic stages, which leads to a smaller clock distribution network. The capability of reducing the number of stages is essential to improve flexibility in the number of logic stages of designed circuits. The method introduces more clockless gates into the resultant netlist compared with our previous method instead of a longer clock period. It utilizes a specific library of supergates, that is, small single-output circuits with several logic gates, used in technology mapping. The library is generated by adding supergates that utilize clockless gates, except for their output parts, to an original library with no clockless gates. The method reduces the number of clocked gates to a greater extent than our previous method and gives designers a higher degree of flexibility in the number of logic stages. The evaluation results indicate that the number of clocked gates in netlists and logic stages is reduced by over 40% when compared with netlists without clockless gates.

关键词： logic gates Libraries Clocks logic Superconductivity logic functions Design tools Hardware design languages Throughput Symbols Design automation logic circuits rapid single flux quantum (RSFQ) logic superconducting integrated circuits

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Systematic Generation of Memristor-Transistor Single-Phase Combinational logic Cells

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第10期43卷 2990-3003页

作者： Biswas, Baishakhi Rani Yuan, Claire Wang, Fangzhou Gupta, Sandeep Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90089 USA

The objective of our research is to create efficient methods and tools for the quick and thorough assessment of emerging digital circuit devices, facilitating the adoption of promising ones. In this work, we develop methods and tools for hybrid technology that combines memristors with MOS transistors and demonstrates their effectiveness. Although several types of memristor-transistor logic have been proposed, 15 years of research has created a small set of logic cells. We propose a systematic method for generating new and efficient memristor-transistor single-phase combinational logic cells. At the core of our approach is a cell enumerator, which enables us to explore a wide range of cell designs, including nonintuitive ones, and a data-driven inductive learning method, which identifies new properties of such cells and scales up our explorations. In conjunction with other completely new tools, these create a comprehensive and definitive library of logic cells. Our new cells provide significant improvements or significantly distinct Pareto-optimal alternatives for the few logic functions for which prior research has created cells. Importantly, our methods enable us to discover a previously unknown synergistic operation between memristors and transistors that occurs for specific cell topologies. We harness this synergy to develop a method for adding memristors to low-area pass-transistor circuits such that they produce strong output voltages and low power, including for patterns that cause ratioed operation. We have also developed a new memristor-transistor logic family, namely controlled-AND (cAND)/controlled-OR (cOR), which includes many of the best cells. We have also developed a constructive method for designing such cells.

关键词： Memristors Voltage MOSFET logic functions Libraries Databases Reviews Data-driven inductive learning (IL) enumeration logic cells memristors

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State Estimation of Stochastic Boolean Networks Based on Event-Triggered Sampling

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IEEE TRANSACTIONS ON SYSTEMS MAN CYBERNETICS-SYSTEMS 2025年

作者： Wei, Zibo Ding, Yong Guo, Yuqian Gui, Weihua Cent South Univ Sch Automat Changsha 410083 Peoples R China Nanchang Univ Sch Informat Engn Nanchang 330031 Peoples R China

A stochastic Boolean network (SBN) emerges as a more realistic model for gene regulatory networks than a deterministic Boolean network (BN). In order to reduce output sampling while ensuring a given estimation accuracy, this article proposes an event-triggered sampling strategy for the state estimation of SBNs. Under this strategy, the output is sampled when the one-step prediction mean error exceeds a prespecified threshold. An iterative algorithm for the state probability distribution is proposed based on the algebraic form of SBNs, which determines the optimal state estimation. A matrix inequality method is proposed to calculate the worst-case mean estimation error based on its monotonicity with time. Then, the range of sampling triggering thresholds that minimize the worst-case mean estimation error is obtained. This article demonstrates that the event-triggered sampling strategy can make a tradeoff between estimation error and sampling rate. It explains that the full sampling estimator is a special event-triggered sampling estimator. Finally, the proposed method is applied to BN models of the lac operon in Escherichia coli to analyze the relationship among the sampling triggering threshold, the sampling rate, and the estimation error.

关键词： Vectors State estimation Event detection Estimation error Uncertainty Stochastic processes Noise logic functions Iterative methods Escherichia coli Event-triggered sampling semi-tensor product (STP) state estimation stochastic Boolean networks (SBNs)

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Development and analysis of all-optical multipurpose OR, XOR, NAND, AND, NOR, and XNOR logic gates in a single unit using silicon microring resonator

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OPTICAL AND QUANTUM ELECTRONICS 2024年第5期56卷 1-17页

作者： Hossain, Manjur Basha, S. Mahaboob Nagaraju, V. Mondal, Kalimuddin Rakshit, Jayanta Kumar Saveetha Inst Med & Tech Sci Saveetha Sch Engn Chennai 602105 India Natl Inst Technol Agartala Dept Elect & Instrumentat Engn Agartala 799046 India

There is a rising demand for low-cost, high-information-capacity optical signal processing. The number of devices is limited of performing different Boolean functions using a single unit. In the current manuscript, six basic logic gates, including OR, XOR, NAND, AND, NOR, and XNOR, are implemented in a single unit utilizing all-optical silicon microring resonator. At first, three microring resonators are used to get the AND, XOR and NOR logic functions. Then, beam combiners are used to get the OR, NAND and XNOR functions from AND, XOR, and NOR functions. In MATLAB, the suggested design is numerically simulated to verify the functions at an operational speed of nearly 260 Gbps. The required pump power for switching is only 1.95 mW for microring resonator based switch which is very less comparatively. Also, some performance parameters like "extinction ratio", "contrast ratio", "amplitude modulation", "on-off ratio", and "quality factor" are evaluated. To design the circuit practically, optimized parameters of the circuits have been selected. The obtained values of "extinction ratio" and "contrast ratio" are 14.97 dB and 19.03 dB, respectively. The value of AM is 0.17 dB which is less than 1 dB. The on-off ratio of the MRR is 35.10 dB which is much higher than expected.

关键词： Microring resonator (MRR) Multifunction logic functions All-optical switch

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A Systematic Map Method for Realizing Minimal logic functions of Arbitrary Number of Variables

A Systematic Map Method for Realizing Minimal Logic Function...

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International Conference on Circuits, Systems, Communication and Information Technology Applications (CSCITA)

作者： Rathore, Tejmal S. Jain, Ashish St Francis Inst Technol Elect & Telecommun Engn Bombay 400103 Maharashtra India TATA Consultancy London England

ISBN: (纸本)9781479924943

A map method for reducing a logic function to its minimal form is presented. The function of N variables is first mapped into an m X n map such that m + n = N. Next the map size is reduced by 50% rows or columns by eliminating one of the variables at a time vertically or horizontally. The procedure is repeated till the size of the map becomes 1 X 1. Because of the inbuilt simplification of logic expressions, the resulting function is minimal. The method is systematic and definitely leads to the minimal function. It is simpler in operation than that based on only Boolean identities, Karnaugh map and Quine-McCluskey methods. It can handle any number of variables. It is explained with several examples.

关键词： Minimal Realizations logic functions Truth Table Method Digital Circuits Map Method

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An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array

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IEEE TRANSACTIONS ON COMPUTERS 2023年第12期72卷 3416-3430页

作者： Zhang, Sunrui Cui, Xiaole Wei, Feng Cui, Xiaoxin Peking Univ Shenzhen Grad Sch Shenzhen 518055 Peoples R China Peking Univ Inst Microelect Beijing 100871 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China

In-memory computing is an emerging computing paradigm to breakthrough the von-Neumann bottleneck. The SRAM based in-memory computing (SRAM-IMC) attracts great concerns from industries and academia, because the SRAM is technology compatible with the widely-used MOS devices. The digital SRAM-IMC scheme has advantages on stability and accuracy of computing results, compared with the analog SRAM-IMC schemes. However, few logic operations can be implemented by the current digital SRAM-IMC architectures. Designers have to insert some special logic modules to facilitate the complex computation. To address this issue, this work proposes an area-efficient implementation method of arbitrary Boolean function in SRAM array. Firstly, a two-input SRAM LUT is designed to realize the arbitrary two-input Boolean functions. Then, the logic merging and the spatial merging techniques are proposed to reduce the area consumption of the SRAM-IMC scheme. Finally, the SOP-based SRAM-IMC architecture is proposed, and the merged SOPs are mapped into and computed in it. The evaluation results on LGsynth'91, IWLS'93 and EPFL benchmarks show that, the area of the synthesis results based on the ABC tool is 3.69, 5.72 and 1.86 times of the circuit area from the proposed SRAM-IMC scheme in average respectively. Furthermore, the circuit area from the original SOP-based SRAM-IMC scheme is 2.07, 1.99 and 1.86 times in average of the circuit area from the proposed SRAM-IMC scheme respectively. The performance evaluation results show that the cycle consumption of the proposed SRAM-IMC scheme is independent to the scale of the input Boolean functions.

关键词： Random access memory Computer architecture Table lookup Merging Parallel processing SRAM cells logic functions Arbitrary Boolean functions in-memory computing SRAM synthesis method

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Realization of Complete Boolean logic and Combinational logic Functionalities on a Memristor-Based Universal logic Circuit

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Chinese Journal of Electronics 2024年第5期33卷 1137-1146页

作者： Xiaojuan LIAN Chuanyang SUN Zeheng TAO Xiang WAN Xiaoyan LIU Zhikuang CAI Lei WANG College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications

Memristors are a promising solution for building an advanced computing system due to their excellent characteristics, including small energy consumption, high integration density, fast write/read speed, great endurance and so on. In this work, we firstly design three basis logic XNOR1, XNOR2 and XOR gates by virtue of memristor ratioed logic(MRL), and further construct 1-bit numerical comparators, 2-bit numerical comparators and full adder 1 based on the above XNOR1, XNOR2 and XOR gates. Furthermore, we propose and design a universal logic circuit that can realize four different kinds of logic functions(AND, OR, XOR, XNOR) at the same time. Subsequently, a full adder 2 is built using XOR function of this universal logic circuit. Compared with the traditional CMOS circuits,the universal logic circuit designed in this work exhibits several merits such as fewer components, less power, and lower delay. This work demonstrates that memristors can be used as a potential solution for building a novel computing architecture.

关键词： Power demand logic circuits Buildings Memristors logic gates logic functions Software

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The ECCANDE Project: Design, Field Implementation, and Operation of a Special Protection Scheme Based on Synchronized Phasor Measurements

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IEEE TRANSACTIONS ON POWER DELIVERY 2023年第3期38卷 1780-1787页

作者： Godoy, Jose Maria Barua de Oliveira, Robson Almir Aguayo, Gustavo Rodriguez, Elisandro Szostak, Alfredo Javier Mezger Santos, Jhonatan Andrade dos Tochetto, Andre Pagani Rios, Manuel Leonardo Sosa Galassi, Paulo Henrique Pesente, Jonas Roberto Ramos, Rodrigo Andrade ANDE Asuncion 1409 Paraguay Itaipu Binacl Syst Operat BR-85856970 Foz Do Iguacu PR Brazil Univ Sao Paulo Elect Engn BR-13566590 Sao Carlos SP Brazil

This paper presents the ECCANDE project, one of the first Special Protection Schemes (SPS) conceived to rely on the structure of a Wide-Area Monitoring, Protection, and Control System (WAMPACS) and currently operating in a real, large-sized power system. This project was developed and implemented to enable the interconnection between the Argentinean and Paraguayan bulk power transmission systems, which involves and directly affects two of the largest hydropower plants in the world (the Itaipu and Yacyreta power plants). Building this WAMPACS-based SPS took more than a decade of work performed by multiple teams, involving modeling, planning studies, design, manufacturing, real-time hardware-in-the-loop (HIL) simulation for equipment testing, implementation, commissioning, field tests and evaluation of daily operation. The paper describes how system stability problems (detected during the initial studies for the interconnection) made it clear that the ECCANDE SPS had to be a WAMPACS-based one, and how its architecture and logic functions were conceived to deal with these problems. The results of HIL real-time simulations and a main field test show that the ECCANDE SPS enabled the interconnection, successfully protecting against the loss of synchronism between the Itaipu and Yacyreta power plants before the system separation.

关键词： Power system stability Real-time systems Power generation Substations Phasor measurement units logic functions Transmission line measurements WAMPACS Synchronized Phasor Measurement Systems PMUs Special Protection Scheme Paraguayan-Argentinean Interconnection

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Using Approximate Circuits Against Hardware Trojans

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2023年第3期40卷 8-16页

作者： Martin, Honorio Dupuis, Sophie Di Natale, Giorgio Entrena, Luis Univ Carlos III Madrid Dept Elect Technol Madrid 28911 Spain Univ Montpellier LIRMM CNRS Montpellier France Univ Grenoble Alpes TIMA CNRS Grenoble INP F-38031 Grenoble France

Editor's notes: Approximate computing is almost always associated with results showing a tradeoff between accuracy and computational efficiency. In this article, however, approximate computing finds application in... 详细信息

关键词： Circuit faults Tools Integrated circuit modeling Trojan horses Sensitivity Redundancy logic functions Design-for-Hardware-Trust Hardware Trojan Approximation

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A Survey of Majority logic Designs in Emerging Nanotechnologies for Computing

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2023年 22卷 732-739页

作者： Zhang, Tingting Jiang, Honglan Liu, Weiqiang Lombardi, Fabrizio Liu, Leibo Ko, Seok-Bum Han, Jie Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 1H9 Canada Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai 200240 Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 211106 Peoples R China Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Tsinghua Univ Inst Microelect Beijing Natl Res Ctr Informat Sci & Technol Beijing 100084 Peoples R China Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK S7N 5C9 Canada

As Moore's law is coming to an end, research on technologies alternative to the complementary metal-oxide semiconductor (CMOS) has been extensively pursued over the last few decades. Many emerging nanotechnologies assemble circuits based on majority logic. It is generally known that majority logic is more expressive and hardware efficient than Boolean logic, however majority logic presents unique challenges at many levels such as arithmetic design and synthesis. With the rediscovery of majority logic as a computational primitive in the post-CMOS era, this article briefly reviews recent studies from various perspectives to highlight accomplishments and open problems across many domains of majority logic design.

关键词： logic gates Magnetic tunneling Plasmons logic functions Quantum dots Memristors Magnetostatics Majority logic logic synthesis approximate computing nanotechnology reliability

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