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The Synthesis Method of logic Circuits Based on the NMOS-Like RRAM Gates

IEEE ACCESS 2021年 9卷 54466-54477页

作者： Cui, Xiaole Ma, Ye Wei, Feng Cui, Xiaoxin Peking Univ Key Lab Integrated Microsyst Shenzhen Grad Sch Shenzhen 518055 Peoples R China Peking Univ Inst Microelect Beijing 100871 Peoples R China

The synthesis method of logic circuits based on the RRAM (Resistive Random Access Memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like RRAM gate family. The advantages of the proposed NMOS-like RRAM gates include: (1) all the gate circuits are array-implementable;(2) the gate family is logic complete;(3) the NOR, AND and NOT gates only consume single cycle respectively in the computation phase;(4) the gate circuits save half number of RRAM devices compared with the CMOS-like RRAM based counterparts. Furthermore, the synthesis method of logic circuits based on the NMOS-like RRAM gates is proposed and discussed. The single-cycle NMOS-like RRAM gates are utilized in priority under the constraints of the logic block. The features of the proposed synthesis method are: (1) it generates the high-performance logic circuits because the NMOS-like RRAM based gates work in parallel;(2) the logic block based on the proposed NMOS-like gates can be realized in the RRAM array;(3) the large-scale logic functions can be implemented by cascading the logic blocks. The in-array full-adder circuit generated by the proposed synthesis method only consumes three cycles in minimum, which outperforms the previous RRAM based counterpart. The synthesis results on the benchmark circuits show that the proposed synthesis method is able to generate the high-performance circuit in RRAM arrays for arbitrary logic functions.

关键词： logic gates Resistance logic arrays Random access memory logic functions Electrodes RRAM array NMOS-like RRAM gates computation in memory synthesis method

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A systematic map method for realizing minimal logic functions of arbitrary number of variables

A systematic map method for realizing minimal logic function...

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International Conference on Circuits, Systems, Communication and Information Technology Applications (CSCITA)

作者： Tejmal S. Rathore Ashish Jain Electronics & Telecommunication Engineering St Francis Institute of Technology Mumbai India TATA Consultancy London UK

A map method for reducing a logic function to its minimal form is presented. The function of N variables is first mapped into an m× n map such that m + n = N. Next the map size is reduced by 50% rows or columns by eliminating one of the variables at a time vertically or horizontally. The procedure is repeated till the size of the map becomes 1×1. Because of the inbuilt simplification of logic expressions, the resulting function is minimal. The method is systematic and definitely leads to the minimal function. It is simpler in operation than that based on only Boolean identities, Karnaugh map and Quine-McCluskey methods. It can handle any number of variables. It is explained with several examples.

关键词： Information technology logic functions Systematics Conferences Communications technology Roads Digital circuits

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Multilayer Nanomagnet Threshold logic

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2021年第4期68卷 1944-1949页

作者： Zhou, Peng Gnoli, Luca Sadriwala, Mustafa M. Riente, Fabrizio Turvani, Giovanna Hassan, Naimul Hu, Xuan Vacca, Marco Friedman, Joseph S. Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA Politecn Torino Elect & Telecommun Dept I-10129 Turin Italy

Nanomagnet logic (NML) uses dipolar magnetic coupling between nanomagnets to efficiently perform nonvolatile logical operations. As the basis logic element, the three-input minority gate is the simplest threshold logic function. Recent work has explored the potential for increased logical expressivity with a nanomagnet threshold logic family that reduces area, delay, and energy costs. However, as such previous work was limited to a single layer of nanomagnets, only negative input weights could be provided, thus limiting circuit expressivity and efficiency. This article therefore, proposes multilayer nanomagnet threshold logic systems that provide both positive and negative weights by leveraging multilayer structures that produce both ferromagnetic and antiferromagnetic dipolar coupling. The availability of both positive and negative weights drastically increases logical expressivity, and the feasibility of the proposed multilayer nanomagnet threshold logic system is demonstrated through micromagnetic simulations. A single seven-input gate is shown to perform more than 86 distinct logic functions, reducing the number of gates and clock cycles required for complex logic circuits by as much as 67%.

关键词： logic gates Magnetic multilayers Couplings Nonhomogeneous media Magnetization Magnetic circuits logic functions Multilayer logic nanomagnet logic (NML) perpendicular magnets threshold logic

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Integrating Two logics Into One Crossbar Array for logic Gate Design

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2021年第8期68卷 2987-2991页

作者： Yao, Lian Liu, Peng Wu, Jigang Han, Yinhe Zhong, Yuehang You, Zhiqiang Guangdong Univ Technol Sch Comp Sci & Technol Ctr High Performance Comp & Data Sci Guangzhou 510006 Guangdong Peoples R China Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing 100190 Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Key Lab Embedded Changsha 410082 Peoples R China Hunan Univ Network Comp Hunan Prov Changsha 410082 Peoples R China

Memristor-based crossbar array is one of the most promising structure for in-memory computing platforms. In a crossbar array, material implication logic (IMPLY) can be performed between different word lines or bit lines. Not-material implication (N-IMPLY) can only be performed between the bit lines. This brief demonstrates the feasibility of the execution of N-IMPLY logic between the word lines, followed by an approach for logic gate design in which two logics IMPLY and N-IMPLY are integrated into one crossbar array. Both two logics can be performed between the cells in different rows and columns within the crossbar. Six basic Boolean gates are implemented utilizing the proposed approach, with a lower number of operation steps and memristors compared to the IMPLY-only method. Moreover, a 1-bit full adder is implemented by utilizing the designed logic gates. The performance and area overhead have been improved by the proposed approach, in comparison to the existing methods.

关键词： logic gates Memristors logic arrays Resistance logic functions Adders Switches logic gates memristive crossbar material implication not material implication 1-bit full adder

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An Energy Efficient In-Memory Computing Architecture Using Reconfigurable Magnetic logic Circuits for Big Data Processing

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IEEE TRANSACTIONS ON MAGNETICS 2023年第12期59卷 1页

作者： Gargari, Milad Ashtari Eslami, Nima Moaiyeri, Mohammad Hossein Shahid Beheshti Univ Fac Elect Engn Tehran *** Iran

In-memory computing (IMC) is considered one of the most promising candidates to solve the nontraditional challenges conventional computing systems face in dealing with novel big data applications. This article proposes an efficient hybrid magnetic tunnel junction (MTJ)/FinFET base IMC architecture performing all basic Boolean logic operations (AND/NAND, OR/NOR, XOR/XNOR) in only one system clock. To this end, a novel memory cell design based on in-plane anisotropy MTJ (I-MTJ) is proposed, which can perform various logic operations in the memory array. In the proposed array, various logic operations can benefit from connecting I-MTJ memory cells in series in the selected column and a novel sense amplifier (SA) unit. Moreover, the full adder (FA) operation is accomplished by exploiting the Majority logic function, which indicates its functionality mostly in a ripple carry adder (RCA) implementation that requires only n + 2 clock cycles for n-bit calculation. The circuit-level simulations indicate that the proposed design improves energy consumption of performing the AND/NAND and OR/NOR operations by approximately 80%, the XOR/XNOR operations by 79%, and the FA operation by 47% compared to its state-of-the-art counterparts. Moreover, the Monte Carlo simulations authenticate the high robustness of the proposed architecture in the presence of process variations. To validate the proposed design's efficiency in real-world applications, the minimum/maximum image filters, as the essential preprocessing steps in widely used applications like optical character recognition (OCR) and the VGG-16 neural network with the ImageNet dataset, are implemented using the proposed IMC architecture.

关键词： Computer architecture Magnetic tunneling Microprocessors Random access memory Resistance logic functions In-memory computing Big data in-plane anisotropy MTJ (I-MTJ) in-memory computing (IMC) magnetic logic

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Methodology for Distributed-ROM-Based Implementation of Finite State Machines

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2021年第11期40卷 2411-2415页

作者： Senhadji-Navarro, Raouf Garcia-Vargas, Ignacio Univ Seville Dept Comp Architecture & Technol E-41012 Seville Spain

This brief explores the optimization of distributed-ROM-based finite state machine (FSM) implementations as an alternative to conventional implementations based on look-up tables (LUTs). In distributed-ROM implementations, LUTs with constant output value (called constant LUTs) and LUTs with the same content (called equivalent LUTs) can be saved. We propose a methodology to implement FSMs using distributed ROM that includes: 1) a greedy state encoding algorithm;2) an algorithm to find the way of interconnecting the address signals to the ROM that maximize the number of constant or equivalent LUTs;and 3) a set of architectures to implement the columns of the ROM. The results obtained have been compared with conventional LUT-based implementations using standard benchmarks. The proposed technique reduces the number of LUTs in a 91% of cases and increases the speed in all cases.

关键词： Table lookup Read only memory Multiplexing Field programmable gate arrays Encoding Optimization logic functions Distributed ROM finite state machine (FSM) FPGA ROM-based implementation

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Design of Area-Efficient Memristor-Based XOR and XNOR Gates

Design of Area-Efficient Memristor-Based XOR and XNOR Gates

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International Conference on Radioelektronika

作者： Ananda Y. R. Subhashis Das Gaurav Trivedi Dept. of ECE IIIT Bangalore Bengaluru India Physical Design Qualcomm Hyderabad India Dept. of EEE IIT Guwahati Guwahati India

ISBN: (数字)9798331544478

ISBN: (纸本)9798331544485

This paper presents the novel area-efficient and optimized hybrid XOR and XNOR gates designed using four MOSFETs (two NMOS and two PMOS transistors) and four memristors. This work employs the Yakopcic memristor model and $TSMC\ 180\ nm$ CMOS PDKs for MOSFETs to design the logic circuits. The logic function of the proposed XOR and XNOR gates are verified using LTSPICE, and the valid logic outputs are obtained for all the input combinations. The effectiveness of the proposed XOR and XNOR gates is validated by simulating a full adder and a 2-bit magnitude comparator using LTSPICE.

关键词： Semiconductor device modeling Degradation MOSFET Memristors Voltage logic gates Numerical simulation logic functions Nanoscale devices Adders

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Memristive logic-in-Memory Implementation with Area Efficiency and Parallelism

Memristive Logic-in-Memory Implementation with Area Efficien...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Ikkyum Kim Heechun Park Department of Electrical Engineering Ulsan National Institute of Science and Technology (UNIST) Ulsan Korea

ISBN: (数字)9798350380408

ISBN: (纸本)9798350380415

In-memory computing that performs logic operations inside the memory unit has emerged as an alternative to the traditional von Neumann architecture. In particular, logic-in-memory (LiM) architecture with memristor crossbars shows promising results in terms of power and performance, which operates the Boolean functions within the crossbar in parallel by utilizing memristor-aided logic (MAGIC) operations. In this work, we propose an efficient LUT mapping framework of Boolean logic functions into the memristor crossbar, which leverages the parallelism of logic computation to maximize performance and enhances area efficiency by optimizing crossbar utility. In detail, we map the LUTs of NoN (NOR-of-NOR) into the crossbar in a topological order in a way that maximizes the horizontal and vertical NOR operations. Moreover, we add an algorithmic rearranging stage for the intermediate results to more utilize the crossbar space during the next LUT placement. Our experiments prove that the proposed LUT mapping framework incorporates parallel operations with higher area efficiency, thereby achieving a 13.81 % speedup on average with a smaller crossbar dimension compared to the previous approach. We also successfully map the benchmark circuits with a large number of LUTs into the small-sized crossbar, in which the previous method has failed.

关键词： Circuits Memristors Computer architecture Parallel processing Benchmark testing logic functions In-memory computing Table lookup Computational efficiency logic

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Controllability-Based Circuit Similarity Estimation

Controllability-Based Circuit Similarity Estimation

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IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Michal Žáček Petr Fišer Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Prague Czech Republic

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Assessing the structural similarity of different implementations of logic functions is of importance in many areas of digital design, such as iterative resynthesis, engineering change order (ECO) based design, design of reliable redundant systems (duplex, TMR), etc. In general, numerous metrics exist that describe such similarity, mostly based on its intended application. In this paper, we introduce a novel metric based on a calculation of the functional equivalence of subcircuits. As this approach requires repeated calls of time-consuming functional equivalence checking, we propose a linear-time approximation of this method based on signal controllability calculation. These two approaches are compared to the state-of-the-art fault detection-based design diversity estimation technique and applied to assess the fault-security capabilities of duplex systems.

关键词： Measurement Fault detection Estimation Reliability engineering logic functions Electrical fault detection Controllability Iterative methods Integrated circuit reliability Electronic circuits

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Hardware Implementation of an Adaptive Finite State Machine Utilizing Tsetlin Machine

Hardware Implementation of an Adaptive Finite State Machine ...

引用

Tsetlin Machine (ISTM), International Symposium on the

作者： Yehuda Rudin Osnat Keren Michal Yemini Alex Fish Faculty of Engineering Bar Ilan University Ramat Gan Israel

ISBN: (数字)9798331504984

ISBN: (纸本)9798331504991

In many applications, the deployed system is required to adjust to unpredictable changes in environments and real-time circumstances. Finite State Machine (FSM) is a computational model that is widely used for control in digital designs. In this study, we assume that the FSM behavioral model ought to adapt to a changing environment, whose characteristics are unknown in advance. To achieve this goal, instead of synthesizing the combinational logic from a predefined behavioral model, we utilize Tsetlin Machine (TM) design to construct the targeted logic functions through learning. The paper presents an approach to hardware implementation of a TM-based adaptive FSM that can be applied to ASIC. The implementation is validated and tested on an FPGA platform. The data collected from the measurements provides valuable insights into the learning process, such as the connection between the organization of the clauses that are formed by the TM and the resulting learning rate.

关键词： Adaptation models Computational modeling Learning automata Automata Organizations logic functions Hardware Real-time systems logic Field programmable gate arrays

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