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检索条件"主题词=Logic functions"

共 2086 条记录，以下是61-70 订阅

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Controllability-Based Circuit Similarity Estimation

Controllability-Based Circuit Similarity Estimation

引用

IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Michal Žáček Petr Fišer Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Prague Czech Republic

ISBN: (数字)9798331528010

ISBN: (纸本)9798331528027

Assessing the structural similarity of different implementations of logic functions is of importance in many areas of digital design, such as iterative resynthesis, engineering change order (ECO) based design, design of reliable redundant systems (duplex, TMR), etc. In general, numerous metrics exist that describe such similarity, mostly based on its intended application. In this paper, we introduce a novel metric based on a calculation of the functional equivalence of subcircuits. As this approach requires repeated calls of time-consuming functional equivalence checking, we propose a linear-time approximation of this method based on signal controllability calculation. These two approaches are compared to the state-of-the-art fault detection-based design diversity estimation technique and applied to assess the fault-security capabilities of duplex systems.

关键词： Measurement Fault detection Estimation Reliability engineering logic functions Electrical fault detection Controllability Iterative methods Integrated circuit reliability Electronic circuits

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Hardware Implementation of an Adaptive Finite State Machine Utilizing Tsetlin Machine

Hardware Implementation of an Adaptive Finite State Machine ...

引用

Tsetlin Machine (ISTM), International Symposium on the

作者： Yehuda Rudin Osnat Keren Michal Yemini Alex Fish Faculty of Engineering Bar Ilan University Ramat Gan Israel

ISBN: (数字)9798331504984

ISBN: (纸本)9798331504991

In many applications, the deployed system is required to adjust to unpredictable changes in environments and real-time circumstances. Finite State Machine (FSM) is a computational model that is widely used for control in digital designs. In this study, we assume that the FSM behavioral model ought to adapt to a changing environment, whose characteristics are unknown in advance. To achieve this goal, instead of synthesizing the combinational logic from a predefined behavioral model, we utilize Tsetlin Machine (TM) design to construct the targeted logic functions through learning. The paper presents an approach to hardware implementation of a TM-based adaptive FSM that can be applied to ASIC. The implementation is validated and tested on an FPGA platform. The data collected from the measurements provides valuable insights into the learning process, such as the connection between the organization of the clauses that are formed by the TM and the resulting learning rate.

关键词： Adaptation models Computational modeling Learning automata Automata Organizations logic functions Hardware Real-time systems logic Field programmable gate arrays

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Design Of Performance Improved 4-Bit Baugh Wooley Multiplier Using LUT

Design Of Performance Improved 4-Bit Baugh Wooley Multiplier...

引用

International Conference on Power, Energy, Control and Transmission Systems (ICPECTS)

作者： S. Saranya G. Sudha Janarthanarajan S Bhuvanesh T Karthikeyan M Department of Electronics and Communication Engineering Sri Sairam Engineering College Chennai India

ISBN: (数字)9798331508845

ISBN: (纸本)9798331508852

In the realm of digital design, the multiplication operation stands as a fundamental yet computationally intensive task, often requiring dedicated hardware solutions for efficient execution. In this context, the utilization of Look-Up Tables (LUTs) within Xilinx Field-Programmable Gate Arrays (FPGAs) emerges as a promising avenue for implementing high-performance multipliers. This project aims to explore and develop a LUT-based multiplier design using Xilinx technology, leveraging FPGAs' inherent flexibility and configurability to achieve optimized performance metrics. The proposed multiplier design harnesses the computational power of LUTs, which serve as configurable memory elements capable of implementing complex logic functions. Through careful architectural design and optimization techniques, the project seeks to maximize the efficiency of the multiplier while minimizing resource utilization and latency. By exploiting the parallelism inherent in FPGA architectures, the multiplier aims to deliver accelerated multiplication operations, catering to diverse application requirements across various domains. The project endeavors to explore potential enhancements and optimizations, such as pipelining, parallel processing, and resource sharing, to further improve the speed and efficiency of the multiplier implementation. Through iterative refinement and experimentation, the aim is to achieve a balance between performance, resource utilization, and power efficiency, thereby demonstrating the practical viability and applicability of the LUT-based multiplier design in real-world applications.

关键词： Measurement Computer architecture logic functions Table lookup Computational efficiency Resource management Iterative methods Field programmable gate arrays Optimization Pipeline processing

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Towards Fast Automatic Design of Silicon Dangling Bond logic

Towards Fast Automatic Design of Silicon Dangling Bond Logic

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Jan Drewniok Marcel Walter Samuel Sze Hang Ng Konrad Walus Robert Wille Chair for Design Automation Technical University of Munich Germany Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada Software Competence Center Hagenberg GmbH Austria

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology. Unlike conventional circuit technology, where logic is realized through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, logic functions can be constructed. However, determining such arrangements is a tremendously complex task. Because of that, the automatic obtainment of SiDB logic implementations is inefficient. To address this challenge, we propose an idea to speed up the design process by utilizing dedicated search space pruning strategies. Initial results show that the combined pruning techniques yield 1) a drastic reduction of the search space, and 2) a corresponding reduction in runtime by up to a factor of 33.

关键词： Runtime Quantum dots Europe logic gates logic functions Silicon logic Transistors Standards

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Synthesis of LUT Networks for Random-Looking Dense functions with Don't Cares — Towards Efficient FPGA Implementation of DNN

Synthesis of LUT Networks for Random-Looking Dense Functions...

引用

Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Yukio Miyasaka Alan Mishchenko John Wawrzynek Nicholas J. Fraser University of California Berkeley California USA AMD Research and Advanced Development Dublin Ireland

ISBN: (数字)9798350372434

ISBN: (纸本)9798350372441

Many EDA applications deal with logic functions representing complex mathematical computations. Although in many cases, these functions depend on a small number of inputs, they often resemble random functions, making it hard to synthesize them using the traditional methods based on SOP minimization. This paper describes efficient synthesis and LUT mapping for this class of functions using a novel method that implements BDD-based minimization based on truth tables. The paper also investigates optimization with don't cares, when the outputs of a function are unspecified for some inputs, which is particularly useful in machine learning applications that trade accuracy for area. Compared to optimization and mapping used in academic and industrial tools, our method works faster and results in 1.5x smaller networks, while extra 20% area reduction was possible with don't cares at almost no accuracy cost.

关键词： Accuracy Neural networks Machine learning Minimization logic functions Table lookup logic

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An Improved Lower Bound on the Gate Count of Toffoli-Based Reversible logic Circuits

An Improved Lower Bound on the Gate Count of Toffoli-Based R...

引用

International Symposium on Multiple-Valued logic

作者： Takashi Hirayama Ryo Endo Katsuhisa Yamanaka Department of Systems Innovation Engineering Iwate University Morioka Japan

ISBN: (数字)9798350343083

ISBN: (纸本)9798350343090

This paper presents an improved lower bound, denoted as $v$ , on the number of gates in Toffoli-based reversible circuits that realize a given reversible logic function. The previous lower bound $\sigma-lb$ used the characteristic vectors of reversible functions to formulate the theory of lower bounds. We carefully investigate cofactors of reversible functions to refine the characteristic vectors, and obtain a new theoretical basis for improving lower bounds. We show that the proposed lower bound $v$ is better than the previous lower bound $\sigma-lb$ by making both mathematical and experimental comparisons. Although the gain of refinement is not so significant in the experiments, an improvement of lower bounds is valuable as a theoretical achievement.

关键词： logic circuits logic gates Minimization logic functions Vectors

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A Campus Local Area Network Architecture based on Software Defined Networking

A Campus Local Area Network Architecture based on Software D...

引用

Next Generation Data-driven Networks (NGDN), International Conference on

作者： Minggui Chen Yaqi Gu Yangrui Zhang Qi Qu Lanzhou 95950 Research Institute Lanzhou China

ISBN: (数字)9798350388374

ISBN: (纸本)9798350388381

The communication network within the campus has always adopted the traditional distributed network control architecture to meet the high reliability, high availability and low latency requirements of the network. However, as the demand for rapid network activation continues to emerge, the traditional distributed network control architecture has shown many shortcomings such as closed network architecture and difficulty in network deployment, resulting in a situation where the network is difficult to expand and management is complex and difficult. In response to the above problems, this paper proposes a campus local area network architecture based on software-defined network, using software-defined network technology ideas to transform the existing campus network. Through the open southbound control interface design, the control and forwarding logic functions are decoupled. Centralized control is used to give the network a global view, improve network management and control capabilities, and meet the needs of flexible network provisioning in heterogeneous networks.

关键词： Computer architecture Transforms Network architecture logic functions Planning Communication networks Software defined networking Local area networks Next generation networking Centralized control

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Contrastive Learning in Memristor-Based Neuromorphic Systems

Contrastive Learning in Memristor-Based Neuromorphic Systems

引用

IEEE Workshop on Signal Processing Systems (SIPS)

作者： Cory Merkel Alexander G. Ororbia Brain Lab Rochester Institute of Technology Rochester NY Neural Adaptive Computing Lab Rochester Institute of Technology Rochester NY

ISBN: (数字)9798350373752

ISBN: (纸本)9798350373769

Spiking neural networks have become an important family of neuron-based models that sidestep many of the key limitations facing modern-day backpropagation-trained deep networks, including their high energy inefficiency and long-criticized biological implausibility. In this work, we design and investigate a proof-of-concept instantiation of contrastive-signal-dependent plasticity (CSDP), a neuromorphic form of forward-forward-based, backpropagation-free learning. Our experimental simulations demonstrate that a hardware implementation of CSDP is capable of learning simple logic functions without the need to resort to complex gradient calculations.

关键词： Neuromorphics Biological system modeling Current measurement Neurons Contrastive learning Spiking neural networks Signal processing logic functions Hardware Synapses

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Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning

Thinking Outside the Clock: Physical Design for Field-couple...

引用

IEEE International Symposium on Quality Electronic Design

作者： Simon Hofmann Marcel Walter Lorenzo Servadei Robert Wille Chair for Design Automation Technical University of Munich Germany Software Competence Center Hagenberg GmbH Austria

ISBN: (数字)9798350309270

ISBN: (纸本)9798350309287

Recent advances in atom-scale manufacturing are paving the way toward the emergence of Field-coupled Nanocomputing (FCN) as a viable real-world post-CMOS technology. Current FCN-specific solutions for placement and routing of logic functions are at risk of falling behind manufacturing capabilities. The problem lies in the fact that existing algorithms are either optimal in their result quality but do not scale; or are scalable, but produce results of sub-par quality limited to select clocking schemes. Furthermore, most existing approaches are tailored toward a concrete FCN implementation, limiting their applicability across the domain. To address these challenges, we propose a novel approach that utilizes deep reinforcement learning to learn the placement of logic elements and incorporate established routing strategies directly into the placement step. By relying only on abstract signal flow directions, this solution is technology-agnostic and therefore applicable to any FCN implementation, layout topology, or clocking scheme. The proposed approach is experimentally evaluated on a set of established benchmark functions common in the domain. While a state-of-the-art exact approach is limited to designing layouts for functions containing a maximum of around 40 gates, the proposed approach is able to generate solutions for all functions included in the considered benchmark sets, while reducing the layout area by an average of 59% compared to the state-of-the-art heuristic. Furthermore, the proposed algorithm is made available to the scientific community as an open-source implementation.

关键词： Limiting Layout logic gates Benchmark testing Routing logic functions Deep reinforcement learning

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Compact Write-Based Computing-in-Memory (CIM) Using High Speed Switching (HSS) MRAM

Compact Write-Based Computing-in-Memory (CIM) Using High Spe...

引用

Electronic Technology and Information Science (ICETIS), International Conference on

作者： Yang Lu Zhi Yuan Wang Ye Cheng Yang Shao Hao Wang FZU-Jinjiang Joint Institute of Microelectronics Jinjiang Science and Education Park Fuzhou University Fujian Jinjiang China

ISBN: (数字)9798350388343

ISBN: (纸本)9798350388350

Magnetic random-access memory (MRAM)-based computing-in-memory (CIM) schemes can be divided into write-based CIM and read-based CIM. Compared with read-based CIM, the write-based CIM can perform more operations such as AND, OR, majority (MAJ) gate, and full adder (FA). However, write-based CIM schemes require a large number of memory cells and multiple processing cycles. In this paper, we proposed a compact write-based CIM scheme by using a one transistor one high-speed switch magnetic tunnel junction (IT-IHSS-MTJ) memory cell to implement NAND, NOR, XOR, and MAJ gates within two write cycles and one read cycle. Moreover, we also demonstrated that FA operation can also be performed using three 1 T-IHSS-MTJ cells within six cycles. According to the simulation results performed using the SMIC 40 nm CMOS process and the HSS-MTJ SPICE model, we have demonstrated that these logic functions can be achieved. When compared to the write-based CIM using SOT-MRAM, the proposed CIM requires fewer cells and shorter latency to achieve the same logic operations.

关键词： Semiconductor device modeling Simulation Computational modeling logic gates In-memory computing SPICE logic functions

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