For mesh-based Network-on-Chip (NoC), in order for a routing algorithm to be implemented by logic-based circuit, the prohibited turns should be repetitively distributed. The 3D mesh network has a huge searching space ...
详细信息
ISBN:
(纸本)9781450369497
For mesh-based Network-on-Chip (NoC), in order for a routing algorithm to be implemented by logic-based circuit, the prohibited turns should be repetitively distributed. The 3D mesh network has a huge searching space for routing algorithms. Due to its complexity, there is lack of research to detect its design space. In this paper, the design space for logic-based routing algorithms for 3D mesh network is systematically exploited. After detecting the design space, new logic-based routing algorithm that outperforms the state-of-the-art routing algorithms is proposed. For the first step, all routing algorithms that have repetitively distributed turns for 2D mesh network are constructed. For the second step, the routing algorithms for the three planes of the 3D mesh network are constructed respectively. The Z plane of the 3D mesh network is constructed by placing a 2D network routing on it. The X and Y planes of the 3D mesh network are constructed by rotating the Z plane up or down, respectively. Finally, the constructed routing algorithms are evaluated under 44 traffic scenarios. The best routing algorithm is termed as 3D repetitive turn model (3DRTM). Simulation results show that it has better performance than the prior proposed routing algorithm under most synthetic and real traffic scenarios.
Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-awareness is a new challenge present in NoCs that must be efficiently handled by the routing functionality as it introduces irregular...
详细信息
Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-awareness is a new challenge present in NoCs that must be efficiently handled by the routing functionality as it introduces irregularities in the commonly used 2-D meshes. In this article, we propose a logic-based routing algorithm, iFDOR, oriented towards dynamic powering down one region within every application partition on the chip through dynamic rerouting, with low implementation costs. Results show that we can successfully shutdown an arbitrary rectangular region within an application partition without significant impact on network performance.
At the core of an efficient chip multiprocessors (CMP) is support for unicast and multicast routing, low implementation costs, and the ability to isolate concurrent applications with maximum utilization of the CMP. We...
详细信息
At the core of an efficient chip multiprocessors (CMP) is support for unicast and multicast routing, low implementation costs, and the ability to isolate concurrent applications with maximum utilization of the CMP. We present an efficient logic-based unicast and multicast routing algorithm that guarantees isolation of local application traffic within any near-convex region on the chip, and the algorithms to recognize supported partitions and configure the cores accordingly. Evaluations show that the routing algorithm has a 57% more compact implementation than a recent multicast solution with the same coverage, and it achieves 5% higher throughput with 13% lower latency.
For 2D mesh based Network-on-Chip (NoC), the prohibited turns of routing algorithms should be repetitively distributed in order for the routing algorithms to be implemented by logic-based circuit. In this paper, we ai...
详细信息
For 2D mesh based Network-on-Chip (NoC), the prohibited turns of routing algorithms should be repetitively distributed in order for the routing algorithms to be implemented by logic-based circuit. In this paper, we aim to exploit the designing space for logic-based routing algorithms, and propose new logic-based routing algorithms that outperform the state-of-the-art counterparts. Toward this direction, we firstly construct all routing algorithms for 5 x 5 2D mesh topology. Then we select those routing algorithms which have repetitive prohibited turns across both the network rows and columns. In addition, we chose those routing algorithms that have smaller routing pressures than Odd-Even routing algorithm. Then the routing algorithms for 2D mesh topology ranging from 6 x 6 to 15 x 15 are respectively constructed according to the prohibited turns distribution of the selected routing algorithms. Two routing algorithms that have smaller routing pressures than Odd-Even routing algorithm are obtained for all considered networks. The obtained logic-based routing algorithms are called as Repetitive Turn Model (RTM). Simulation results show that RTM could achieve up to 51% performance improvement as compared to Odd-Even routing algorithm.
For 2D mesh based Network-on-Chip(NoC), the o1 turn routing algorithm is proposed to achieve near-optimal worst-case throughput. RTM routing has the best routing performance among all those routings which have repetit...
详细信息
For 2D mesh based Network-on-Chip(NoC), the o1 turn routing algorithm is proposed to achieve near-optimal worst-case throughput. RTM routing has the best routing performance among all those routings which have repetitive prohibited turns. In this paper, detailed simulations are conducted to compare these two routing algorithms. Simulation results show that RTM routing has better performance than o1 turn routing under most traffic scenarios. O1 turn routing's performance improve quickly when more virtual channels are implemented.
暂无评论