检索结果-内蒙古大学图书馆

An object-oriented framework for loop parallelization

JOURNAL OF SUPERCOMPUTING 1999年第1期13卷 57-69页

作者： Omori, Y Fukuda, A Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300101 Japan Wakayama Univ Fac Syst Engn Wakayama 6408441 Japan

Generation of efficient parallel code is a major goal of a well-designed and developed parallelizing compiler. Another important goal is portability of both compiler system and the resulting output source codes. The various choices of current and future parallel computer architectures as well as the cost of developing a parallelizing compiler make portability a very important design goal. Since the design of parallelizing compilers is considerably move complex than designing conventional compilers, it is very important to achieve both efficiency and portability. To meet this dual goal, we have investigated the application of object oriented design to parallelizing compilers. Our parallelizing compiler design is based on abstractions of intermediate representations of loops and their class definitions. In this paper, we address the problem of loop parallelization and propose a framework where the loop parallelization process is divided into three phases and the optimization of loops is performed via a cyclic application of these three phases. The class of each phase is hierarchically derived from intermediate representations of loops. This facilitates the portability of the resulting parallelizing compilers. Furthermore, one of the phases uses a reservation table of hardware resources in order to obtain optimized parallel programs for given hardware resources. The validation of the proposed framework is given through the application of the object oriented design on an example program which is then parallelized efficiently.

关键词： object-oriented design parallelizing compiler loop parallelization OMT portability

来源：评论

学校读者我要写书评

暂无评论

DEPENDENCE UNIFORMIZATION - A loop parallelization TECHNIQUE

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1993年第5期4卷 547-558页

作者： TZEN, TH NI, LM MICHIGAN STATE UNIV DEPT COMP SCIE LANSINGMI 48824

In general, any nested loop can be parallelized as long as all dependence constraints among iterations are preserved by applying appropriate synchronizations. However, the performance is significantly affected by the synchronization overhead. In case of irregular and complex dependence constraints, it is very difficult to efficiently and systematically arrange synchronization primitives. In this paper, we propose a new method, data dependence uniformization, to overcome the difficulties in parallelizing a doubly nested loop with irregular dependence constraints. Our approach is based on the concept of vector decomposition. A simple set of basic dependences is developed of which all dependence constraints can be composed. The set of basic dependences then will be added to every iteration to replace all original dependences so that the dependence constraints become uniform. Finally, an efficient synchronization method is presented to obey the uniform dependence constraints in every iteration.

关键词： DEPENDENCE CONSTRAINT loop ITERATION loop parallelization PARALLELIZING COMPILER PROCESS SYNCHRONIZATION VECTOR DECOMPOSITION

来源：评论

学校读者我要写书评

暂无评论

Using knowledge-based techniques on loop parallelization for parallelizing compilers

引用

PARALLEL COMPUTING 1997年第3期23卷 291-309页

作者： Yang, CT Tseng, SS Chuang, CD Shih, WC NATL CHIAO TUNG UNIV DEPT COMP & INFORMAT SCIHSINCHU 300TAIWAN

In this paper we propose a knowledge-based approach for solving data dependence testing and loop scheduling problems. A rule-based system, called the K-Test, is developed by repertory grid and attribute ording table to construct the knowledge base. The K-Test chooses an appropriate testing algorithm according to some features of the input program by using knowledge-based techniques, and then applies the resulting test to detect data dependences for loop parallelization. Another rule-based system, called the KPLS, is also proposed to be able to choose an appropriate scheduling by inferring some features of loops and assign parallel loops on multiprocessors for achieving high speedup. The experimental results show that the graceful speedup obtained by our compiler is obvious.

关键词： parallelizing compiler data dependence testing loop parallelization parallel loop scheduling knowledge-based repertory grid analysis speedup

来源：评论

学校读者我要写书评

暂无评论

Quantifier elimination in automatic loop parallelization

引用

JOURNAL OF SYMBOLIC COMPUTATION 2006年第11期41卷 1206-1221页

作者： Groesslinger, Armin Griebl, Martin Lengauer, Christian Univ Passau Dept Math & Informat D-94030 Passau Germany

We present an application of quantifier elimination techniques in the automatic parallelization of nested loop programs. The technical goal is to simplify affine inequalities whose coefficients may be unevaluated symbolic constants. The values of these so-called structure parameters are determined at run time and reflect the problem size. Our purpose here is to make the research community of quantifier elimination, in a tutorial style, aware of our application domain-loop parallelization-and to highlight the role of quantifier elimination, as opposed to alternative techniques, in this domain. Technically, we focus on the elimination method of Weispfenning. (c) 2006 Elsevier Ltd. All rights reserved.

关键词： loop parallelization quantifier elimination

来源：评论

学校读者我要写书评

暂无评论

An Implementation of LLVM Pass for loop parallelization Based on IR-Level Directives 6

An Implementation of LLVM Pass for Loop Parallelization Base...

引用

6th International Symposium on Computing and Networking (CANDAR) - Across Practical Development and Theoretical Research

作者： Jingu, Kengo Shigenobu, Kohta Ootsu, Kanemitsu Ohkawa, Takeshi Yokota, Takashi Utsunomiya Univ Grad Sch Engn Utsunomiya Tochigi Japan

ISBN: (纸本)9781538691847

Currently, multicore processors are widely used, and processing performance can be improved on many machines by exploiting thread level parallelism. However, for parallelizing a program, it takes much time and effort to analyze effect of parallel processing and to rewrite the source code, so sequential programs still remain around the world, and they can not fully bring out performance of multicore processors. To improve execution performance of existing sequential programs by effectively utilizing processing power of multicore processors, it is quite useful to automatically and directly parallelize a machine language code (binary code) by using binary translation. Based on this background, an automatic parallel processing system that parallelizes and optimizes a sequential binary code using LLVM was proposed. In this paper, we introduce parallelization directives for LLVM IR (Intermediate Representation), and implement an LLVM compiler pass for parallel code generation based on the directives. Our research makes it possible to implement analysis and code generation as versatile programs, and to generate an optimal code according to the multiple analysis results. Evaluation results show that the implemented pass can generate a parallelized IR code and can achieve speedup as highly as the parallelization using source code does.

关键词： LLVM loop parallelization IR code parallelization directives

来源：评论

学校读者我要写书评

暂无评论

Validation of loop parallelization and loop Vectorization Transformations 11

Validation of Loop Parallelization and Loop Vectorization Tr...

引用

11th International Conference on Evaluation of Novel Software Approaches to Software Engineering

作者： Dutta, Sudakshina Sarkar, Dipankar Rawat, Arvind Singh, Kulwant Indian Inst Technol Kharagpur Kharagpur W Bengal India

ISBN: (纸本)9789897581892

loop parallelization and loop vectorization of array-intensive programs are two common transformations applied by parallelizing compilers to convert a sequential program into a parallel program. Validation of such transformations carried out by untrusted compilers are extremely useful. This paper proposes a novel algorithm for construction of the dependence graph of the generated parallel programs. The transformations are then validated by checking equivalence of the dependence graphs of the original sequential program and the parallel program using a standard and fairly general algorithm reported elsewhere in the literature. The above equivalence checker still works even when the above parallelizing transformations are preceded by various enabling transformations except for loop collapsing which changes the dimensions of the arrays. To address the issue, the present work expands the scope of the checker to handle this special case by informing it of the correspondence between the index spaces of the corresponding arrays in the sequential and the parallel programs. The augmented algorithm is able to validate a large class of static affine programs. The proposed methods are implemented and tested against a set of available benchmark programs which are parallelized by the polyhedral auto-parallelizer loopo and the auto-vectorizer Scout. During experiments, a bug of the compiler loopo on loop parallelization has been detected.

关键词： loop parallelization loop Vectorization Dependence Graph Conflict Access Validation

来源：评论

学校读者我要写书评

暂无评论

Map-Reduce Inspired loop parallelization on CGRA

Map-Reduce Inspired Loop Parallelization on CGRA

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Shao, Shengjia Yin, Shouyi Liu, Leibo Wei, Shaojun Tsinghua Univ Dept Microelect Beijing 100084 Peoples R China

ISBN: (纸本)9781479934324

Our work(1) investigates how to map loops efficiently onto Coarse Grained Reconfigurable Architecture (CGRA). This paper examines the properties of CGRA and builds Map-Reduce inspired models for the loop parallelization problem. We solve our model using Geometric Programming methods to obtain best loop unrolling parameters. Those parameters are used in the Back-End process that followed. Experiment results show the proposed approach achieved up to 44% performance gain compared to a state-of-the-art loop unrolling scheme.

关键词： Map-Reduce CGRA loop parallelization

来源：评论

学校读者我要写书评

暂无评论

Data distribution and loop parallelization for shared-memory multiprocessors 9th

引用

Proceedings of the 1996 9th International Workshop on Languages and Compilers for Parallel Computing

作者： Ayguade, E. Garcia, J. Grande, M.L. Labarta, J. Computer Architecture Department Polytechnic University of Catalunya cr. Gran Capità s/núm Mòdul D6 Barcelona 08034 Spain

ISBN: (纸本)3540630910

Shared-memory multiprocessor systems can achieve high performance levels when appropriate work parallelization and data distribution are performed. These two actions are not independent and decisions have to be taken in a unified way trying to minimize execution time and data movement costs. The first goal is achieved by parallelizing loops (the main components suitable for parallel execution in scientific codes) and assign work to processors having in mind a good load balancing. The second goal is achieved when data is stored in the cache memories of processors minimizing both true and false sharing of cache lines. This paper describes the main features of our automatic parallelization and data distribution research tool and shows the performance of the parallelization strategies generated. The tool (named PDDT) accepts programs written in Fortran77 and generates directives of shared memory programming models (like Power Fortran from SGI or Exemplar from Convex).

关键词： High Performance Compilers loop parallelization Static and Dynamic Data Mappings Cache Behavior Shared Memory Multiprocessors

来源：评论

学校读者我要写书评

暂无评论

Run-time support to register allocation for loop parallelization of image processing programs 8th

引用

8th International Conference on High Performance Computing and Networking

作者： Zingirian, N Maresca, M Univ Padua Dipartimento Elettron & Informat I-35131 Padua Italy

ISBN: (纸本)3540675531

When Image Processing Programs (IPP) are targeted to Instruction Level Parallel architectures that perform dynamic instruction scheduling, register allocation is the key action to expose the high parallelism degree typically present in the loops of such programs. This paper presents two main contributions to the register allocation for IPP loop parallelization: i) a framework to identify the inefficiencies of the two basic approaches to register allocation - the first based on compiling techniques and the second based on hardware mechanisms for register renaming;ii) a novel technique that eliminates the inefficiencies of both approaches. Some experimental results show the effectiveness of this technique.

关键词： dynamic register renaming image processing instruction level parallelism loop parallelization register allocation

来源：评论

学校读者我要写书评

暂无评论

Improving loop parallelization by a Combination of Static and Dynamic Analyses in HLS

引用

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2022年第3期15卷 31-31页

作者： Dewald, Florian Rohde, Johanna Hochberger, Christian Mantel, Heiko Tech Univ Darmstadt Dept Comp Sci Hochschulstr 10 D-64289 Darmstadt Germany Tech Univ Darmstadt Comp Syst Grp Merckstr 25 D-64283 Darmstadt Germany

High-level synthesis (HLS) can be used to create hardware accelerators for compute-intense software parts such as loop structures. Usually, this process requires significant amount of user interaction to steer kernel selection and optimizations. This can be tedious and time-consuming. In this article, we present an approach that fully autonomously finds independent loop iterations and reductions to create parallelized accelerators. We combine static analysis with information available only at runtime to maximize the parallelism exploited by the created accelerators. For loops wherewe see potential for parallelism, we create fully parallelized kernel implementations. If static information does not suffice to deduce independence, thenwe assume independence at compile time. We verify this assumption by statically created checks that are dynamically evaluated at runtime, before using the optimized kernel. Evaluating our approach, we can generate speedups for five out of seven benchmarks. With four loop iterations running in parallel, we achieve ideal speedups of up to 4x and on average speedups of 2.27x, both in comparison to an unoptimized accelerator.

关键词： FPGA system-on-chip high-level synthesis scalar evolution analysis loop parallelization

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：