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Improving loop parallelization by a Combination of Static and Dynamic Analyses in HLS

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2022年第3期15卷 31-31页

作者： Dewald, Florian Rohde, Johanna Hochberger, Christian Mantel, Heiko Tech Univ Darmstadt Dept Comp Sci Hochschulstr 10 D-64289 Darmstadt Germany Tech Univ Darmstadt Comp Syst Grp Merckstr 25 D-64283 Darmstadt Germany

High-level synthesis (HLS) can be used to create hardware accelerators for compute-intense software parts such as loop structures. Usually, this process requires significant amount of user interaction to steer kernel selection and optimizations. This can be tedious and time-consuming. In this article, we present an approach that fully autonomously finds independent loop iterations and reductions to create parallelized accelerators. We combine static analysis with information available only at runtime to maximize the parallelism exploited by the created accelerators. For loops wherewe see potential for parallelism, we create fully parallelized kernel implementations. If static information does not suffice to deduce independence, thenwe assume independence at compile time. We verify this assumption by statically created checks that are dynamically evaluated at runtime, before using the optimized kernel. Evaluating our approach, we can generate speedups for five out of seven benchmarks. With four loop iterations running in parallel, we achieve ideal speedups of up to 4x and on average speedups of 2.27x, both in comparison to an unoptimized accelerator.

关键词： FPGA system-on-chip high-level synthesis scalar evolution analysis loop parallelization

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An Implementation of LLVM Pass for loop parallelization Based on IR-Level Directives 6

An Implementation of LLVM Pass for Loop Parallelization Base...

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6th International Symposium on Computing and Networking (CANDAR) - Across Practical Development and Theoretical Research

作者： Jingu, Kengo Shigenobu, Kohta Ootsu, Kanemitsu Ohkawa, Takeshi Yokota, Takashi Utsunomiya Univ Grad Sch Engn Utsunomiya Tochigi Japan

ISBN: (纸本)9781538691847

Currently, multicore processors are widely used, and processing performance can be improved on many machines by exploiting thread level parallelism. However, for parallelizing a program, it takes much time and effort to analyze effect of parallel processing and to rewrite the source code, so sequential programs still remain around the world, and they can not fully bring out performance of multicore processors. To improve execution performance of existing sequential programs by effectively utilizing processing power of multicore processors, it is quite useful to automatically and directly parallelize a machine language code (binary code) by using binary translation. Based on this background, an automatic parallel processing system that parallelizes and optimizes a sequential binary code using LLVM was proposed. In this paper, we introduce parallelization directives for LLVM IR (Intermediate Representation), and implement an LLVM compiler pass for parallel code generation based on the directives. Our research makes it possible to implement analysis and code generation as versatile programs, and to generate an optimal code according to the multiple analysis results. Evaluation results show that the implemented pass can generate a parallelized IR code and can achieve speedup as highly as the parallelization using source code does.

关键词： LLVM loop parallelization IR code parallelization directives

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Validation of loop parallelization and loop Vectorization Transformations 11

Validation of Loop Parallelization and Loop Vectorization Tr...

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11th International Conference on Evaluation of Novel Software Approaches to Software Engineering

作者： Dutta, Sudakshina Sarkar, Dipankar Rawat, Arvind Singh, Kulwant Indian Inst Technol Kharagpur Kharagpur W Bengal India

ISBN: (纸本)9789897581892

loop parallelization and loop vectorization of array-intensive programs are two common transformations applied by parallelizing compilers to convert a sequential program into a parallel program. Validation of such transformations carried out by untrusted compilers are extremely useful. This paper proposes a novel algorithm for construction of the dependence graph of the generated parallel programs. The transformations are then validated by checking equivalence of the dependence graphs of the original sequential program and the parallel program using a standard and fairly general algorithm reported elsewhere in the literature. The above equivalence checker still works even when the above parallelizing transformations are preceded by various enabling transformations except for loop collapsing which changes the dimensions of the arrays. To address the issue, the present work expands the scope of the checker to handle this special case by informing it of the correspondence between the index spaces of the corresponding arrays in the sequential and the parallel programs. The augmented algorithm is able to validate a large class of static affine programs. The proposed methods are implemented and tested against a set of available benchmark programs which are parallelized by the polyhedral auto-parallelizer loopo and the auto-vectorizer Scout. During experiments, a bug of the compiler loopo on loop parallelization has been detected.

关键词： loop parallelization loop Vectorization Dependence Graph Conflict Access Validation

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A Survey of loop parallelization: Models, Approaches, and Recent Developments

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INTERNATIONAL JOURNAL OF GRID AND DISTRIBUTED COMPUTING 2016年第11期9卷 143-156页

作者： Yao, Hong Deng, Huifang Zou, Caifeng South China Univ Technol Sch Comp Sci & Engn Guangzhou 510006 Guangdong Peoples R China

In cloud computing era, automatic parallelization is still significant for virtualization platform. However, after several decades of development, the overall effect is still to be improved. Summary of the mainstream technology developments will be beneficial to reveal the future direction and trend. This paper reviews the technology of loop parallelization, which is the key issue in automatic parallelization. After introducing the basic models and approaches, we focus on the recent developments, on which we obtain the trend of this field and the conclusions about future.

关键词： Automatic parallelization loop parallelization loop transformation Data dependence Polyhedral model Program dependence graph

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How to Speed up Embedded Multi-core Systems Using Locality Conscious Array Distribution for loop parallelization

How to Speed up Embedded Multi-core Systems Using Locality C...

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ARCS 2016;29th International Conference on Architecture of Computing Systems

作者： Niklas Hehenkamp Remko van Wagensveld Dominik Schoenwetter Christian Facchi Ulrich Margull Dietmar Fey Ralph Mader Technische Hochschule Ingolstadt Chair of Computer Science 3 (Computer Architecture) Friedrich-Alexander-University Erlangen-Nurnberg (FAU) Continental Automotive GmbH

Safety critical embedded systems in the automotive domain will increasingly depend on parallel processing architectures. Since concurrency has largely been exploited on task level, future applications will feature growing proportions of parallel implementations on data level such as loop parallelism. Efficient memory utilization becomes inevitable to overcome future challenges facing the memory wall in modern computing. This work suggests an approach for data locality conscious memory accessing and data distribution implementations in embedded multi-core systems. The results have been validated by a case study on a modern Engine Control Unit focusing on the parallelization of widely spread array intensive loops.

关键词： Memory access Multi-core loop parallelization Embedded system Embedded systems parallelization loops data layer memory utilization Consciousness locality data Contraceptive Coil Concurrency Speeding embedding

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Map-Reduce Inspired loop parallelization on CGRA

Map-Reduce Inspired Loop Parallelization on CGRA

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Shao, Shengjia Yin, Shouyi Liu, Leibo Wei, Shaojun Tsinghua Univ Dept Microelect Beijing 100084 Peoples R China

ISBN: (纸本)9781479934324

Our work(1) investigates how to map loops efficiently onto Coarse Grained Reconfigurable Architecture (CGRA). This paper examines the properties of CGRA and builds Map-Reduce inspired models for the loop parallelization problem. We solve our model using Geometric Programming methods to obtain best loop unrolling parameters. Those parameters are used in the Back-End process that followed. Experiment results show the proposed approach achieved up to 44% performance gain compared to a state-of-the-art loop unrolling scheme.

关键词： Map-Reduce CGRA loop parallelization

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Map-Reduce Inspired loop parallelization on CGRA

Map-Reduce Inspired Loop Parallelization on CGRA

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IEEE International Symposium on Circuits and Systems

作者： Shengjia Shao Shouyi Yin Leibo Liu Shaojun Wei Department of Computing Imperial College London London SW7 2AZ UK Department of Microelectronics Tsinghua University Beijing 100084 China

ISBN: (纸本)9781479934331

Our work investigates how to map loops efficiently onto Coarse Grained Reconfigurable Architecture (CGRA). This paper examines the properties of CGRA and builds Map-Reduce inspired models for the loop parallelization problem. We solve our model using Geometric Programming methods to obtain best loop unrolling parameters. Those parameters are used in the Back-End process that followed. Experiment results show the proposed approach achieved up to 44% performance gain compared to a state-of-the-art loop unrolling scheme.

关键词： Map-Reduce CGRA loop parallelization

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Intra-Tile parallelization for Two-Level Perfectly Nested loops With Non-Uniform Dependences

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COMPUTER JOURNAL 2021年第9期64卷 1358-1383页

作者： Reyhan, Zahra Abdi Lotfi, Shahriar Isazadeh, Ayaz Karimpour, Jaber Univ Tabriz Fac Math Sci Dept Comp Sci Tabriz Iran

Most important scientific and engineering applications have complex computations or large data. In all these applications, a huge amount of time is consumed by nested loops. Therefore, loops are the main source of the parallelization of scientific and engineering programs. Many parallelizing compilers focus on parallelization of nested loops with uniform dependences, and parallelization of nested loops with non-uniform dependences has not been extensively investigated. This paper addresses the problem of parallelizing two-level nested loops with non-uniform dependences. The aim is to minimize the execution time by improving the load balancing and minimizing the inter-processor communication. We propose a new tiling algorithm, k-StepIntraTiling, using bin packing problem to minimize the execution time. We demonstrate the effectiveness of the proposed method in several experiments. Simulation and experimental results show that the algorithm effectively reduces the total execution time of several benchmarks compared to the other tiling methods.

关键词： loop parallelization non-uniform dependences two-level perfectly nested loops intra-tiling

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PolyJIT: Polyhedral Optimization Just in Time

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2019年第5-6期47卷 874-906页

作者： Simbuerger, Andreas Apel, Sven Groesslinger, Armin Lengauer, Christian Univ Passau Passau Germany

While polyhedral optimization appeared in mainstream compilers during the past decade, its profitability in scenarios outside its classic domain of linear-algebra programs has remained in question. Recent implementations, such as the LLVM plugin Polly, produce promising speedups, but the restriction to affine loop programs with control flow known at compile time continues to be a limiting factor. PolyJIT combines polyhedral optimization with multi-versioning at run time, at which one has access to knowledge enabling polyhedral optimization, which is not available at compile time. By means of a fully-fledged implementation of a light-weight just-in-time compiler and a series of experiments on a selection of real-world and benchmark programs, we demonstrate that the consideration of run-time knowledge helps in tackling compile-time violations of affinity and, consequently, offers new opportunities of optimization at run time.

关键词： JIT compilation loop parallelization Polyhedron model

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loop Parallelism Maximization for Multimedia Data Processing in Mobile Vehicular Clouds

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IEEE TRANSACTIONS ON CLOUD COMPUTING 2019年第1期7卷 250-258页

作者： Qiu, Meikang Dai, Wenyun Vasilakos, Athanasios V. Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen 518060 Peoples R China Pace Univ Seidenberg Sch Comp Sci & Informat Syst New York NY 10038 USA Univ Western Macedonia Kozani 50100 Greece

Mobile vehicular cloud has become popular with the rapid development of cloud computing and mobile computing. Nested loops are usually the most critical part in multimedia and high performance Digital Signal Processing (DSP) systems which are widely used in vehicular applications and systems. In order to further explore the parallelism in nested loops, we study how to maximize the system performance with considering the energy reduction for applications on Chip Multiprocessor (CMP) architectures. We propose an algorithm Energy-Aware loop Parallelism Maximization (EALPM) to maximize the system performance with the consideration of energy reduction for applications with multidimensional nested loops. Our experiment shows that using the EALPM algorithm significantly improves both performance and energy consumption on average in comparision to other algorithms.

关键词： loop parallelization mobile vehicular cloud energy-aware nested loops multimedia data processing

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