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检索条件"主题词=Loop Parallelization"
69 条 记 录,以下是1-10 订阅
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An object-oriented framework for loop parallelization
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JOURNAL OF SUPERCOMPUTING 1999年 第1期13卷 57-69页
作者: Omori, Y Fukuda, A Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300101 Japan Wakayama Univ Fac Syst Engn Wakayama 6408441 Japan
Generation of efficient parallel code is a major goal of a well-designed and developed parallelizing compiler. Another important goal is portability of both compiler system and the resulting output source codes. The v... 详细信息
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DEPENDENCE UNIFORMIZATION - A loop parallelization TECHNIQUE
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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1993年 第5期4卷 547-558页
作者: TZEN, TH NI, LM MICHIGAN STATE UNIV DEPT COMP SCIE LANSINGMI 48824
In general, any nested loop can be parallelized as long as all dependence constraints among iterations are preserved by applying appropriate synchronizations. However, the performance is significantly affected by the ... 详细信息
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Using knowledge-based techniques on loop parallelization for parallelizing compilers
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PARALLEL COMPUTING 1997年 第3期23卷 291-309页
作者: Yang, CT Tseng, SS Chuang, CD Shih, WC NATL CHIAO TUNG UNIV DEPT COMP & INFORMAT SCIHSINCHU 300TAIWAN
In this paper we propose a knowledge-based approach for solving data dependence testing and loop scheduling problems. A rule-based system, called the K-Test, is developed by repertory grid and attribute ording table t... 详细信息
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Quantifier elimination in automatic loop parallelization
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JOURNAL OF SYMBOLIC COMPUTATION 2006年 第11期41卷 1206-1221页
作者: Groesslinger, Armin Griebl, Martin Lengauer, Christian Univ Passau Dept Math & Informat D-94030 Passau Germany
We present an application of quantifier elimination techniques in the automatic parallelization of nested loop programs. The technical goal is to simplify affine inequalities whose coefficients may be unevaluated symb... 详细信息
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An Implementation of LLVM Pass for loop parallelization Based on IR-Level Directives  6
An Implementation of LLVM Pass for Loop Parallelization Base...
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6th International Symposium on Computing and Networking (CANDAR) - Across Practical Development and Theoretical Research
作者: Jingu, Kengo Shigenobu, Kohta Ootsu, Kanemitsu Ohkawa, Takeshi Yokota, Takashi Utsunomiya Univ Grad Sch Engn Utsunomiya Tochigi Japan
Currently, multicore processors are widely used, and processing performance can be improved on many machines by exploiting thread level parallelism. However, for parallelizing a program, it takes much time and effort ... 详细信息
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Validation of loop parallelization and loop Vectorization Transformations  11
Validation of Loop Parallelization and Loop Vectorization Tr...
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11th International Conference on Evaluation of Novel Software Approaches to Software Engineering
作者: Dutta, Sudakshina Sarkar, Dipankar Rawat, Arvind Singh, Kulwant Indian Inst Technol Kharagpur Kharagpur W Bengal India
loop parallelization and loop vectorization of array-intensive programs are two common transformations applied by parallelizing compilers to convert a sequential program into a parallel program. Validation of such tra... 详细信息
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Map-Reduce Inspired loop parallelization on CGRA
Map-Reduce Inspired Loop Parallelization on CGRA
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IEEE International Symposium on Circuits and Systems (ISCAS)
作者: Shao, Shengjia Yin, Shouyi Liu, Leibo Wei, Shaojun Tsinghua Univ Dept Microelect Beijing 100084 Peoples R China
Our work(1) investigates how to map loops efficiently onto Coarse Grained Reconfigurable Architecture (CGRA). This paper examines the properties of CGRA and builds Map-Reduce inspired models for the loop parallelizati... 详细信息
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Data distribution and loop parallelization for shared-memory multiprocessors  9th
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Proceedings of the 1996 9th International Workshop on Languages and Compilers for Parallel Computing
作者: Ayguade, E. Garcia, J. Grande, M.L. Labarta, J. Computer Architecture Department Polytechnic University of Catalunya cr. Gran Capità s/núm Mòdul D6 Barcelona 08034 Spain
Shared-memory multiprocessor systems can achieve high performance levels when appropriate work parallelization and data distribution are performed. These two actions are not independent and decisions have to be taken ... 详细信息
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Run-time support to register allocation for loop parallelization of image processing programs  8th
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8th International Conference on High Performance Computing and Networking
作者: Zingirian, N Maresca, M Univ Padua Dipartimento Elettron & Informat I-35131 Padua Italy
When Image Processing Programs (IPP) are targeted to Instruction Level Parallel architectures that perform dynamic instruction scheduling, register allocation is the key action to expose the high parallelism degree ty... 详细信息
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Improving loop parallelization by a Combination of Static and Dynamic Analyses in HLS
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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2022年 第3期15卷 31-31页
作者: Dewald, Florian Rohde, Johanna Hochberger, Christian Mantel, Heiko Tech Univ Darmstadt Dept Comp Sci Hochschulstr 10 D-64289 Darmstadt Germany Tech Univ Darmstadt Comp Syst Grp Merckstr 25 D-64283 Darmstadt Germany
High-level synthesis (HLS) can be used to create hardware accelerators for compute-intense software parts such as loop structures. Usually, this process requires significant amount of user interaction to steer kernel ... 详细信息
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