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low-complexity architecture for AR(1) inference

ELECTRONICS LETTERS 2020年第14期56卷 732-733页

作者： Borges, A. Cintra, R. J. Coelho, D. F. G. Dimitrov, V. S. Universidade Federal de Pernambuco Recife Brazil Independent Researcher Calgary Canada University of Calgary Calgary Canada

In this Letter, the authors propose a low-complexity estimator for the correlation coefficient based on the signed AR(1) process. The introduced approximation is suitable for implementation in low-power hardware architectures. Monte Carlo simulations reveal that the proposed estimator performs comparably to the competing methods in the literature with maximum error in order of 10(-2). However, the hardware implementation of the introduced method presents considerable advantages in several relevant metrics, offering more than 95% reduction in dynamic power and doubling the maximum operating frequency when compared to the reference method.

关键词： Monte Carlo methods low-complexity architecture low-complexity estimator correlation coefficient introduced approximation low-power hardware architectures Monte Carlo simulations estimator performs hardware implementation dynamic power maximum operating frequency

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low-complexity Decoding architecture for Rate-Compatible Puncturing Polar Codes 17

Low-Complexity Decoding Architecture for Rate-Compatible Pun...

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IEEE 17th International Conference on Communication Technology (ICCT)

作者： Wang, Xinyi Jia, Dai Sun, Ce Huang, Jingxuan Fei, Zesong Beijing Inst Technol Sch Informat & Elect Beijing 100081 Peoples R China

ISBN: (纸本)9781509039449

Polar codes are the first family of codes which can achieve the channel capacity. Motivated by the demand of high speed transmission for 5G communications, researchers are keen to explore efficient decoding architecture for polar codes. In this paper, we propose a low-complexity decoding architecture for rate-compatible puncturing polar (RCPP) codes with two different puncturing methods, quasi-uniform puncturing (QUP) and shortening. By removing the redundant processing elements for the recursive calculation of log-likelihood ratio, the proposed decoding architecture significantly reduces the space complexity and latency with no BLER performance loss. Moreover, we illustrate that the proposed decoding architecture reduces more complexity if two puncturing methods are employed simultaneously, with negligible BLER performance loss.

关键词： polar codes low-complexity architecture successive cancellation (SC) decoding

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A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第12期71卷 5410-5419页

作者： Kim, Jaehee Han, Sangil Kam, Dongyun Kong, Byeong Yong Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea Kongju Natl Univ Div Elect Elect & Control Engn Cheonan 31080 South Korea

The sorting operation plays a vital role in various signal processing applications. However, due to high hardware complexity resulting from a series of comparisons, designing the cost-efficient sorter is one of the crucial requisites for improving the overall system performance. To obtain the cost-efficient sorting architectures constrained to application-specific input/output conditions, this paper presents a systematic design methodology that effectively eliminates dispensable compare-and-swap (CAS) units. Unlike the previous heuristic approaches, the proposed framework iteratively prunes a CAS unit followed by the validation step. The zero-one principle is newly applied to reduce the validation time for the practical convergence time with massive searching iterations. To expand the search space of the proposed framework, furthermore, we introduce new architectural options and pruning methods, allowing the cost-efficient design results even compared to the state-of-the-art solutions. Targeting the constrained sorters for communication systems, numerous case studies show that the proposed framework successfully removes more than half of CAS units in the baseline sorter design, significantly relaxing the area-time complexity, e.g., 35% reduction compared to the state-of-the-art architecture for 16-input metric sorter in the SCL polar decoder.

关键词： Sorting Measurement Decoding Hardware complexity theory Detectors Design methodology Constrained sorter low-complexity architecture VLSI design zero-one principle

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low-complexity Precision-Scalable Multiply-Accumulate Unit architectures for Deep Neural Network Accelerators

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第4期70卷 1610-1614页

作者： Li, Wenjie Hu, Aokun Wang, Gang Xu, Ningyi He, Guanghui Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai 200240 Peoples R China

Precision-scalable deep neural network (DNN) accelerator designs have attracted much research interest. Since the computation of most DNNs is dominated by multiply-accumulate (MAC) operations, designing efficient precision-scalable MAC (PSMAC) units is of central importance. This brief proposes two low-complexity PSMAC unit architectures based on the well-known one, Fusion Unit (FU), which is composed of a few basic units called Bit Bricks (BBs). We first simplify the architecture of BB through optimizing some redundant logic. Then a top-level architecture for PSMAC unit is devised by recursively employing BBs. Accordingly, two low-complexity PSMAC unit architectures are presented for two different kinds of quantization schemes. Moreover, we provide an insight into the decomposed multiplications and further reduce the bitwidths of the two architectures. Experimental results show that our proposed architectures can save up to 44.18% area cost and 45.45% power consumption when compared with the state-of-the-art design.

关键词： Computer architecture Quantization (signal) Neural networks Costs Throughput Deep learning Adders Deep neural networks (DNNs) multiplyand-accumulate (MAC) precision-scalable low-complexity architecture

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Constrained Sorter Design using Zero-One Principle

Constrained Sorter Design using Zero-One Principle

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Han, Sangil Kim, Jaehee Kam, Dongyun Kong, Byeong Yong Kim, Mijung Kim, Young-Seok Lee, Youngjoo POSTECH Dept Elect Engn Pohang South Korea Samsung Elect Memory Business Hwaseong South Korea Kongju Natl Univ Div Elect Elect & Control Engn Cheonan South Korea POSTECH Sports AIX Grad Program Pohang South Korea

ISBN: (纸本)9798350330991;9798350331004

To derive efficient sorting architectures constrained to application-specific input/output conditions, we present in this paper a systematic design methodology that can effectively prune dispensable compare-and-swap (CAS) units. Unlike the previous works resorting to heuristic approaches, the proposed framework exploits the zero-one principle to validate the pruning of a CAS unit at a time, generating the cost-optimized sorter architecture in an iterative manner with a reasonable complexity. In addition to the given input/output constraints, we newly develop the architecture options for the proposed framework, allowing more design spaces for finding the most attractive constrained-sorter design. For 8-list polar decoders, the proposed framework successfully reduces 70% of CAS units in the baseline full sorter, relaxing the area-time complexity by 35% compared with the state-of-the-art solutions.

关键词： Sorter low-complexity architecture VLSI design zero-one principle

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Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018年第5期26卷 867-877页

作者： Fardad, Mohammad Sayedi, Sayed Masoud Yazdian, Ehsan Isfahan Univ Technol Dept Elect & Comp Engn Esfahan *** Iran

Sparse recovery methods find extensive applications in various fields such as image and audio processing, wireless communication, and spectral estimation. In this paper, a hardware architecture of iterative method with adaptive thresholding (IMAT) is presented to recover a sparse signal from its random samples. To demonstrate the effectiveness of IMAT, a comparison is performed between the IMAT algorithm and the compressive sensing recovery method, orthogonal matching pursuit, in terms of complexity and reconstruction quality. In the context of image reconstruction, as a practical case, simulation results show the advantages of IMAT in improving the performance of the signal reconstruction via peak signal-to-noise ratio and structural similarity index metrics. Since IMAT employs discrete transform as a principal operation in each iteration, using fast or fast approximate algorithms allows more efficient implementation. In this paper, two multiplication-free transforms, Walsh-Hadamard transform (WHT) and approximate discrete cosine transform (ADCT), are used to reduce computational complexity of IMAT implementation. The IMAT recovery algorithm is implemented on Virtex6 FPGA using two above transforms, and the results are compared with respect to the hardware resource utilization, power consumption, and recovery time. The results demonstrate that using WHT for IMAT implementation is more efficient than using ADCT in terms of hardware resources. Also, the comparison implies that the performance of the hardware implementation is very close to its floating point simulated counterpart. For a block size of 32 x 32, the IMAT implementation using WHT provides the reconstruction time of 185 mu s and the dynamic power of 123 mW.

关键词： Discrete transform (DT) hardware reconstruction iterative method with adaptive thresholding (IMAT) low-complexity architecture random sampling

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low-complexity Seizure Prediction From iEEG/sEEG Using Spectral Power and Ratios of Spectral Power

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2016年第3期10卷 693-706页

作者： Zhang, Zisheng Parhi, Keshab K. Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

Prediction of seizures is a difficult problem as the EEG patterns are not wide-sense stationary and change from seizure to seizure, electrode to electrode, and from patient to patient. This paper presents a novel patient-specific algorithm for prediction of seizures in epileptic patients from either one or two single-channel or bipolar channel intra-cranial or scalp electroencephalogram (EEG) recordings with low hardware complexity. Spectral power features are extracted and their ratios are computed. For each channel, a total of 44 features including 8 absolute spectral powers, 8 relative spectral powers and 28 spectral power ratios are extracted every two seconds using a 4-second window with a 50% overlap. These features are then ranked and selected in a patient-specific manner using a two-step feature selection. Selected features are further processed by a second-order Kalman filter and then input to a linear support vector machine (SVM) classifier. The algorithm is tested on the intra-cranial EEG (iEEG) from the Freiburg database and scalp EEG (sEEG) from the MIT Physionet database. The Freiburg database contains 80 seizures among 18 patients in 427 hours of recordings. The MIT EEG database contains 78 seizures from 17 children in 647 hours of recordings. It is shown that the proposed algorithm can achieve a sensitivity of 100% and an average false positive rate (FPR) of 0.0324 per hour for the iEEG (Freiburg) database and a sensitivity of 98.68% and an average FPR of 0.0465 per hour for the sEEG (MIT) database. These results are obtained with leave-one-out cross-validation where the seizure being tested is always left out from the training set. The proposed algorithm also has a low complexity as the spectral powers can be computed using FFT. The area and power consumption of the proposed linear SVM are 2 to 3 orders of magnitude less than a radial basis function kernel SVM (RBF-SVM) classifier. Furthermore, the total energy consumption of a system using linear S

关键词： Branch and bound linear separability low-complexity architecture power spectral density ratio of spectral power seizure prediction two-step feature selection

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Successive Cancellation Heap Polar Decoding 59

Successive Cancellation Heap Polar Decoding

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59th Annual IEEE Global Communications Conference (IEEE GLOBECOM) / Conference on Network Coding and Applications (NetCod)

作者： Zhou, Huayi Liang, Xiao Zhang, Chuan Zhang, Shunqing You, Xiaohu Southeast Univ Natl Mobile Commun Res Lab Nanjing Jiangsu Peoples R China Intel Labs Intel Collaborat Res Inst Mobile Networking Shanghai Peoples R China

ISBN: (纸本)9781509013289

In this paper, the successive cancellation (SC) heap polar decoding scheme is firstly proposed to reduce the complexity. Unlike SC list decoder which keeps L same length paths, SC heap decoding stores different length paths in a heap and always decodes the global optimal path in the root. It has been strictly proved that SC heap decoding is superior to SC stack decoding because the time complexity of inserting new paths is only related to the height of the heap. Proposed SC heap decoding is a dynamic decoding scheme with robustness in various scenarios. Numerical results with binary-input additive white Gaussian noise channel (BI-AWGNC) show that SC heap decoding reduces 63.53% decoding complexity compared with SC list decoding on the same performance at SNR of 2.5 dB. A low-complexity hardware architecture for proposed SC heap decoder is also designed.

关键词： Polar codes successive cancellation heap decoding dynamic scheme low-complexity architecture

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FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第10期23卷 2209-2220页

作者： Rabah, Hassan Amira, Abbes Mohanty, Basant Kumar Almaadeed, Somaya Meher, Pramod Kumar Univ Lorraine Inst Jean Lamour F-54000 Nancy France Qatar Univ Dept Comp Sci & Engn Doha 2713 Qatar Univ West Scotland Sch Engn & Comp Sci Paisley PA1 2BE Renfrew Scotland Jaypee Univ Engn & Technol Dept Elect & Commun Engn Guna 473226 India Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

In this paper, we present a novel architecture based on field-programmable gate arrays (FPGAs) for the reconstruction of compressively sensed signal using the orthogonal matching pursuit (OMP) algorithm. We have analyzed the computational complexities and data dependence between different stages of OMP algorithm to design its architecture that provides higher throughput with less area consumption. Since the solution of least square problem involves a large part of the overall computation time, we have suggested a parallel low-complexity architecture for the solution of the linear system. We have further modeled the proposed design using Simulink and carried out the implementation on FPGA using Xilinx system generator tool. We have presented here a methodology to optimize both area and execution time in Simulink environment. The execution time of the proposed design is reduced by maximizing parallelism by appropriate level of unfolding, while the FPGA resources are reduced by sharing the hardware for matrix-vector multiplication across the data-dependent sections of the algorithm. The hardware implementation on the Virtex6 FPGA provides significantly superior performance in terms of resource utilization measured in the number of occupied slices, and maximum usable frequency compared with the existing implementations. Compared with the existing similar design, the proposed structure involves 328 more DSP48s, but it involves 25 802 less slices and 1.85 times less computation time for signal reconstruction with N = 1024, K = 256, and m = 36, where N is the number of samples, K is the size of the measurement vector, and m is the sparsity. It also provides a higher peak signal-to-noise ratio value of 38.9 dB with a reconstruction time of 0.34 mu s, which is twice faster than the existing design. In addition, we have presented a performance metric to implement the OMP algorithm in resource constrained FPGA for the better quality of signal reconstruction.

关键词： Compressive sensing field-programmable gate array (FPGA) implementation hardware reconstruction low-complexity architecture orthogonal matching pursuit (OMP) algorithm system-level modeling

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Successive Cancellation Heap Polar Decoding

Successive Cancellation Heap Polar Decoding

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IEEE Global Communications Conference

作者： Huayi Zhou Xiao Liang Chuan Zhang Shunqing Zhang Xiaohu You National Mobile Communications Research Laboratory Southeast University Intel Collaborative Research Institutes on Mobile Networking and Computing Intel Labs

ISBN: (纸本)9781509013296

关键词： Polar codes Successive cancellation Heap decoding Dynamic scheme low-complexity architecture

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