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low-complexity error selective Viterbi decoder

ELECTRONICS LETTERS 2000年第2期36卷 147-148页

作者： Sudhakar, R Mukhtar, A Gu, ZZ Florida Atlantic Univ EE Dept Boca Raton FL 33431 USA Motorola Inc IDEN Grp Ft Lauderdale FL 33322 USA

The authors present a low-complexity convolutional decoding scheme, the error selective Viterbi decoder (ESVD), which improves the trellis code search of a conventional Viterbi decoder (VD). Use of the ESVD leads to significant computational savings under typical channel conditions, owing to the isolation of erroneous data stretches and the decoding (only) of the error sequence through a simplified VD search. The effectiveness of multi-bit ESVD schemes is verified for different encoders and data quantisations using Monte Carlo simulations.

关键词： error sequence multi-bit scheme Viterbi decoding low-complexity decoder trellis code search communication complexity Monte Carlo simulations Viterbi decoder Codes trellis codes Monte Carlo methods error selective decoder convolutional codes convolutional decoding scheme Radio links and equipment digital radio

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A complexity-reduced fast successive cancellation list decoder for polar codes

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Science China(Information Sciences) 2018年第2期61卷 138-148页

作者： Qingyun XU Zhiwen PAN Nan LIU Xiaohu YOU National Mobile Communications Research Laboratory Southeast University

A multi-bit decision for polar codes based on a simplified successive cancellation(SSC) decoding algorithm can improve the throughput of polar decoding. A list algorithm is used to improve the errorcorrecting performance. However, list decoders are highly complex compared with decoders without a list algorithm. In this paper, a low-complexity list decoder is proposed, where path-splitting operations for a multi-bit decision can be avoided, if the decoding reliability exceeds a threshold. The threshold is determined based on the reliability of subchannels and positions of decoding nodes. Path splitting rules are designed for multi-bit decision processes, and a complexity-reduced list decoder is proposed based on this. Results show that the number of survival paths can be greatly reduced at the cost of negligible deterioration in block error performance. Thus, the computational complexity can be significantly reduced, especially for a high signal-to-noise ratio(SNR) region.

关键词： polar codes low-complexity decoder splitting-reduced multi-bit decision list decoder

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Power-efficient decoder implementation based on state transparent convolutional codes

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IET CIRCUITS DEVICES & SYSTEMS 2012年第4期6卷 227-234页

作者： Shiau, Y. -H. Yang, H. -Y. Chen, P. -Y. Huang, S. -G. Natl Yunlin Univ Sci & Technol Dept Elect Engn Touliu Taiwan Natl Cheng Kung Univ Dept Comp Sci & Informat Engn Tainan 70101 Taiwan

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

关键词： power saving power-efficient decoder VLSI nonerroneous segments convolutional codes low-complexity decoder state transparent convolutional code decoder segment-based VD erroneous codeword segments clock-gating technique register segments bit reverse decoder Viterbi decoder power-efficient very large-scale integration Viterbi decoding survivor memory unit power consumption

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A low-complexity Design for an MP3 Multi-Channel Audio Decoding System

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IEEE TRANSACTIONS ON AUDIO SPEECH AND LANGUAGE PROCESSING 2012年第1期20卷 314-321页

作者： Moon, Han-Gil Univ Cambridge Dept Expt Psychol Cambridge CB2 3EB England

In this paper, a low complexity design for a DFT-based MP3 multi-channel audio decoding system is proposed. By utilizing the proposed decoding system, the advanced MP3 multi-channel decoder can play high-quality multi-channel audio with low processing power. The MP3 multi-channel system is composed of two components, a parametric multi-channel decoder, and an MP3 decoder. A novel convolution-synthesis method in the transform domain can replace the pseudo-quadrature mirror filter (PQMF) module in the MP3 decoder and several small size discrete Fourier transform (DFT) modules can be used instead of a large-size DFT module in the multi-channel decoder. This combination noticeably reduces computing power without significant loss in the decoded audio signal quality. The effect of the error in the decoded audio signal is analyzed by both objective and subjective methods.

关键词： Convolution-synthesis method low-complexity decoder MP3 MP3 multi-channel parametric multi-channel

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Reconfigurable Intelligent Surface-Assisted Uplink Sparse Code Multiple Access

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IEEE COMMUNICATIONS LETTERS 2021年第6期25卷 2058-2062页

作者： Al-Nahhal, Ibrahim Dobre, Octavia A. Basar, Ertugrul Mem Univ Newfoundland Fac Engn & Appl Sci St John NF A1C 5S7 Canada Koc Univ Dept Elect & Elect Engn CoreLab TR-34450 Istanbul Turkey

Reconfigurable intelligent surface-empowered communication (RIS) and sparse code multiple access (SCMA) are promising candidates for future generations of wireless networks. The former enhances the transmission environments, whereas the latter provides a high spectral efficiency transmission. This letter proposes, for the first time, a low-cost design for RIS-assisted uplink SCMA (SCMA-RIS) scheme to improve the conventional SCMA spectrum efficiency. The message passing algorithm (MPA) is utilized and modified to decode the SCMA-RIS transmitted signals. Moreover, a low-complexity decoder for the SCMA-RIS scheme is proposed to significantly reduce the MPA decoding complexity and improve the bit error rate performance of the conventional SCMA. Monte Carlo simulations and complexity analysis are presented, which support the findings.

关键词： complexity theory Uplink Bit error rate Maximum likelihood decoding Iterative decoding Receivers NOMA Sparse code multiple access (SCMA) reconfigurable intelligent surface (RIS) message passing algorithm (MPA) low-complexity decoder

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An Effective low-complexity Error-Floor lowering Technique for High-Rate QC-LDPC Codes

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IEEE COMMUNICATIONS LETTERS 2018年第10期22卷 1988-1991页

作者： Lee, Huang-Chang Chou, Po-Chiao Ueng, Yeong-Luh Chang Gung Univ Dept Elect Engn Taoyuan 333 Taiwan Taoyuan Chang Gung Mem Hosp Dept Neurol Surg Taoyuan 333 Taiwan Natl Tsing Hua Univ Dept Elect Engn Hsinchu 300 Taiwan MediaTek Inc Hsinchu 30078 Taiwan Natl Tsing Hua Univ Inst Commun Engn Hsinchu 300 Taiwan

This letter presents a low-complexity redecoding-based error-floor lowering technique for quasi-cyclic low-density parity-check codes, where a predetermined set of variable nodes are attenuated before the redecoding. Using a two-stage off-line search, the attenuation set is determined based on the error patterns collected from the standard decoding simulation. It is shown that the error floor can he effectively lowered, and only a negligible amount of complexity is introduced.

关键词： low-complexity decoder low-density parity-check (LDPC) codes error floor

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Lattice-Reduction-Aided Conditional Decoding

Lattice-Reduction-Aided Conditional Decoding

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IEEE Wireless Communications and Networking Conference (WCNC)

作者： Najafi, Hossein Damen, Mohamed Oussama Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781479930838

We introduce a low-complexity decoder with near optimal performance for transmission over multi-antenna systems. By using lattice basis reduction for generating almost orthogonal channel matrix, we enhance the conditional decoding technique to implement a fast yet efficient decoder. The lattice reduction-aided conditional decoder is presented as a general detection technique over fading channels to yield significant savings in complexity while achieving close to Maximum Likelihood (ML) performance. We specifically apply the decoder for two practical schemes, uncoded multi-input multi-output (MIMO) systems and the Golden code. By employing the orthogonality defect factor as a universal measure to select a near-orthogonal channel submatrix for conditional decoding, we implement an almost optimal decoder with linear complexity over quasi-static channels for the Golden code and the four-by-four uncoded MIMO system.

关键词： MIMO communication antenna arrays channel coding computational complexity fading channels matrix algebra maximum likelihood decoding maximum likelihood detection orthogonal codes Golden code MIMO system ML performance fading channel four-by-four uncoded MIMO system general detection technique lattice-reduction-aided conditional decoding linear complexity low-complexity decoder maximum likelihood performance multiantenna system near-orthogonal channel submatrix orthogonal channel matrix orthogonality defect factor quasistatic channel uncoded multi-input multi-output system complexity theory Decoding Fading Lattices MIMO Quadrature amplitude modulation Receiving antennas Fading channels multiple input multiple output systems DECODING linear complexity Receiving antennas orthogonal codes MIMO communication Quadrature amplitude modulation maximum likelihood detection maximum likelihood decoding complexity theory fading color matrix algebra Channel coding Antenna arrays

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A low-complexity Dual Trellis Decoding Algorithm for High-Rate Convolutional Codes

A Low-Complexity Dual Trellis Decoding Algorithm for High-Ra...

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IEEE Wireless Communications and Networking Conference (IEEE WCNC)

作者： Vinh Hoang Son Le Nour, Charbel Abdel Douillard, Catherine Boutillon, Emmanuel IMT Atlantique Lab STICC UMR CNRS 6285 F-29238 Brest France Univ Bretagne Sud Lab STICC UMR CNRS 6285 F-56321 Lorient France

ISBN: (纸本)9781728131061

Decoding using the dual trellis is considered as a potential technique to increase the throughput of soft-input soft-output decoders for high coding rate convolutional codes. However, the dual Log-MAP algorithm suffers from a high decoding complexity. More specifically, the source of complexity comes from the soft-output unit, which has to handle a high number of extrinsic values in parallel. In this paper, we present a new low-complexity sub-optimal decoding algorithm using the dual trellis, namely the dual Max-Log-MAP algorithm, suited for high coding rate convolutional codes. A complexity analysis and simulation results are provided to compare the dual Max-Log-MAP and the dual Log-MAP algorithms. Despite a minor loss of about 0.2 dB in performance, the dual Max-Log-MAP algorithm significantly reduces the decoder complexity and makes it a first-choice algorithm for high-throughput high-rate decoding of convolutional and turbo codes.

关键词： Convolutional codes high coding rate dual trellis high-throughput decoder low-complexity decoder turbo codes

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