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Cooperative Computing System for Heavy-Computation and low-latency processing in Wireless Sensor Networks

SENSORS 2018年第6期18卷 1686-1686页

作者： Jung, Jongtack Lee, Woonghee Kim, Hwangnam Korea Univ Sch Elect Engn Seoul 02841 South Korea

Over the past decades, hardware and software technologies for wireless sensor networks (WSNs) have significantly progressed, and WSNs are widely used in various areas including Internet of Things (IoT). In general, existing WSNs are mainly used for applications that require delay-tolerance and low-computation due to the poor resources of traditional sensor nodes in WSNs. However, compared to the traditional sensor nodes, today's devices for WSNs have more powerful resource. Thus, sensor nodes these days not only conduct sensing and transmitting data to servers but also are able to process many operations, so more diverse applications can be applied to WSNs. Especially, many applications using audio data have been proposed because audio is one of the most widely used data types, and many mobile devices already have a built-in microphone. However, many of the applications have a requirement that heavy-operations should be done by a tight deadline, so it is difficult for a single node in WSNs to run relatively heavy applications by itself. In this paper, to overcome this limitation of WSNs, we propose a new emerging system, Healow, a cooperative computing system for heavy-computation and low-latency processing in WSNs. We designed Healow and carried out the practical implementation on real devices. We confirmed the effectiveness of Healow through various experiments using the real devices and simulations. Using Healow, nodes in WSNs are able to perform heavy-computation processes while satisfying a completion time requirement.

关键词： wireless sensor networks Internet of Things cooperative computing heavy computation low-latency processing audio data processing

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Ultralow-latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2021年第6期29卷 1083-1094页

作者： Kam, Dongyun Yoo, Hoyoung Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea Chungnam Natl Univ Dept Elect Engn Daejeon 34134 South Korea

Achieving the attractive error-correcting capability with a simple decoder structure, the polar code using successive cancellation (SC) decoding is now expected to be installed at the resource-limited IoT or embedded communications. However, the existing SC decoders normally suffer from the long processing latency caused by the serialized processing steps, limiting the practical applications of polar codes. In this article, to solve this latency problem, we present a new low-complexity merging operation that can increase the number of parallel factors for realizing the tree-level parallelism. We also modify the previous pruning method to further reduce the number of visited nodes at the parallel SC decoding scenario. In addition, a novel parallel partial-sum calculator (PSC) architecture is introduced to update partial-sum registers with multiple decoded bits by taking only one processing cycle. Implementation results show that the proposed 8-parallel SC polar decoder in 28-nm CMOS requires only 0.140 mu s to decode a (1024, 512) codeword of 5C system, remarkably reducing the decoding latency when compared to the state-of-the-art designs.

关键词： SC communications low-latency processing parallel decoder polar codes successive-cancellation decoding

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low-latency Unfolded-KES Architecture for Emerging Storage Class Memories

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第6期67卷 2103-2113页

作者： Moon, Seungsik Choe, Jeongwon Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.

关键词： Decoding Iterative decoding Memory management Indexes Delays Acceleration BCH decoding emerging nonvolatile memory error-correction code low-latency processing VLSI

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Ultra-low-latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications

Ultra-Low-Latency Parallel SC Polar Decoding Architecture fo...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Kam, Dongyun Lee, Youngjoo Pohang Univ Sci & Technol Dept Elect Engn Pohang South Korea

ISBN: (纸本)9781728103976

In this paper, we newly present a novel parallel polar decoding architecture that significantly reduces the processing latency for 5G wireless communications. Based on the original decoding tree, the proposed scheme first constructs the small trees that generate multiple soft-decision messages in parallel, potentially reducing the decoding latency compared to the previous serialized schemes. The hard-decision estimates are then calculated at the following merging step to decide the decoded outputs and to update the parallel trees. For each parallel tree, the parallel pruning scheme is newly utilized to further optimize the processing latency. In addition, we introduce an efficient parallel decoder architecture, successfully supporting the proposed low-latency algorithm. Implementation results show that the proposed 8-parallel polar decoder in 65nm CMOS uses only 267ns to decode a (1024, 512) polar codeword of 5G system, which is 1.67 times faster than the state-of-the-art design.

关键词： Polar codes successive-cancellation decoding parallel decoder low-latency processing 5G communications

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Ultra-low-latency LDPC Decoding Architecture Using Reweighted Offset Min-Sum Algorithm 52

Ultra-Low-Latency LDPC Decoding Architecture Using Reweighte...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yun, Sangbu Kam, Dongyun Choe, Jeongwon Kong, Byeong Yong Lee, Youngjoo POSTECH Dept Elect Engn Pohang South Korea Kongju Natl Univ Div Elect Elect & Control Engn Cheonan South Korea

ISBN: (纸本)9781728133201

Due to an iterative nature, a low-density parity-check (LDPC) decoder is associated with a long latency, being a major bottleneck of the baseband processor in wireless communication systems. Based on the practical min-sum (MS) decoding method, in this paper, we present a cost-effective algorithm for reducing the processing latency of LDPC decoders. By checking the number of short-length cycles in the LDPC code structure, the proposed method dynamically changes the reweighting factor at the iterative operations, successfully reducing the average number of iterations. In addition, we present several optimization schemes to mitigate the hardware overheads resulting from the proposed reweighting scheme. In a 65-nm CMOS process, a prototype IEEE 802.11ay LDPC decoder optimized by the proposed schemes reduces the decoding latency by 1.7 times with negligible overheads compared with the contemporary designs.

关键词： Error-correction code LDPC decoding low-latency processing Wireless communications

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Time-Critical Computing on a Single-Chip Massively Parallel Processor

Time-Critical Computing on a Single-Chip Massively Parallel ...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： de Dinechin, Benoit Dupont van Amstel, Duco Poulhies, Marc Lager, Guillaume Kalray SA Montbonnot St Martin France

ISBN: (纸本)9783981537024

The requirement of high performance computing at low power can be met by the parallel execution of an application on a possibly large number of programmable cores. However, the lack of accurate timing properties may prevent parallel execution from being applicable to time-critical applications. We illustrate how this problem has been addressed by suitably designing the architecture, implementation, and programming model, of the Kalray MPPA (R)-256 single-chip many-core processor. The MPPA (R)-256 (Multi-Purpose processing Array) processor integrates 256 processing engine (PE) cores and 32 resource management (RM) cores on a single 28nm CMOS chip. These VLIW cores are distributed across 16 compute clusters and 4 I/O subsystems, each with a locally shared memory. On-chip communication and synchronization are supported by an explicitly addressed dual network-on-chip (NoC), with one node per compute cluster and 4 nodes per I/O subsystem. Off-chip interfaces include DDR, PCI and Ethernet, and a direct access to the NoC for low-latency processing of data streams. The key architectural features that support time-critical applications are timing compositional cores, independent memory banks inside the compute clusters, and the data NoC whose guaranteed services are determined by network calculus. The programming model provides communicators that effectively support distributed computing primitives such as remote writes, barrier synchronizations, active messages, and communication by sampling. POSIX time functions expose synchronous clocks inside compute clusters and mesosynchronous clocks across the MPPA (R)-256 processor.

关键词： multiprocessing systems network-on-chip parallel processing CMOS chip NoC POSIX time functions VLIW cores distributed computing primitives dual network-on-chip high performance computing key architectural features low-latency processing multipurpose processing array processor processing engine cores resource management cores singlechip manycore processor singlechip massively parallel processor synchronous clocks time-critical computing Computational modeling Computer architecture Programming Registers Time factors Timing VLIW

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