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Exploiting Extrinsic Information for Serial map Detection by Utilizing Estimator in Holographic Data Storage Systems

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APPLIED SCIENCES-BASEL 2025年第1期15卷 139-139页

作者： Nguyen, Thien An Lee, Jaejin Soongsil Univ Dept Informat Commun Convergence Technol Seoul 06978 South Korea

In the big data era, data are created in huge volume. This leads to the development of storage devices. Many technologies are proposed for the next generation of storage fields. However, among them, holographic data storage (HDS) has attracted much attention and has been introduced as the promising candidate to meet the increasing demand for capacity and speed. For signal processing, HDS faces two major challenges: inter-page interference (IPI) and two-dimensional (2D) interference. To access the IPI problem, we can use balanced coding, which converts user data into an intensity level with uniformly distributed values for each page. For 2D interference, we can use the equalizer and detection to mitigate the 2D interference. However, the often-used equalizer and detection are methods in wireless communication and only handle the one-dimensional (1D) signal. Thus, we can combine the equalizer, detection, and estimator to reduce 2D interference into 1D interference. In this paper, we proposed a combined model using serial maximum a posteriori (map) detection and estimator to improve the detection of HDS systems. In our proposed model, instead of using an estimator with the Viterbi algorithm to predict the upper-lower interference (UPI) or left-right interference (LRI) and converting the received signal into 1D ISI, we used the estimator to predict the extrinsic information for serial map detection. This preserves the 2D information in the received signal in serial map detection and improves the detection of serial map detection by extrinsic information. The simulation results demonstrate that our proposed model significantly improves the bit-error rate (BER) performance compared to previous studies.

关键词： two-dimensional interference equalizer estimator serial map detection holographic data storage (HDS) map algorithm Viterbi algorithm

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An improved sliding window algorithm for Max-Log-map turbo decoder and its programmable LSI implementation

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IEICE TRANSACTIONS ON ELECTRONICS 2005年第3期E88C卷 403-412页

作者： Gambe, H Tanaka, Y Ohbuchi, K Ishihara, T Li, JF Fujitsu Labs Ltd Kawasaki Kanagawa 2118588 Japan

Thanks to the possibility of being able to implement them in decoders in relatively simple ways, turbo codes are being applied to various areas of engineering. Wireless communications is one of the most important applications, where various types of data communications are required and the speed of information and data capacity need to be changed with different rates of parity bit puncturing being adopted to obtain highly efficient transmission. In such applications, adaptation to various turbo-coding specifications on a real-time basis is needed as well as good bit-error-rate performance. We present a new concept for simplifying metric computation and programmable circuit configurations that focuses on the convolutional decoder, which occupies a significant portion of allocated hardware, and we fundamentally treat a simplified log-domain version of the maximum a posteriori (map) algorithm, usually know as the Max-Log-map (MLM), as a base algorithm. The sliding window method provides an attractive way of computing metric values for the Max-Log-map. However, this algorithm does cause degradation, especially when a high rate code is used, generated by bit puncturing. We propose a new means of avoiding this problem and demonstrate that the sliding window, and a modified version as well as other methods, should be flexibly selected to utilize hardware resources depending on turbo specifications. We demonstrated that our proposed methods provide almost the same BER performance as MLM even when a high rate puncturing rate of 5/6 is applied. Finally, we describe the new hardware architecture that we invented to cope with these programmability issues. We show that a turbo-decoding circuit can be implemented in the processor core and its associated unit to configure an LSI macro circuit. The proposed unit has about 60-K gates. We demonstrate that this architecture can be applied to about the 1.5-Mbps information bit throughput of turbo decoding with a 200-MHz clock cycle, wh

关键词： turbo coding map algorithm Max-Log-map sliding window

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Comparative Study of Simplified map algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2015年第2期81卷 305-320页

作者： Shrestha, Rahul Paily, Roy Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati 781039 Assam India

This paper presents hardware and bit-error-rate (BER) performance analysis of simplified maximum-a-posteriori (map) algorithms based on piece-wise-linear-approximations and Maclaurin-series-expansion for the turbo codes. From this comparative study, a simplified map algorithm with optimal BER performance is selected and an architecture suitable for high speed application is suggested for the design of soft-input-soft-output (SISO) unit. Subsequently, a quantitative model is proposed for estimating the amount of memory required by SISO unit in terms of sliding window size, data width of internal metrics and total number of systematic and parity bits. Thereafter, a non-parallelradix-2 architecture of turbo decoder which incorporates SISO unit and quadratic-permutation-polynomial inter-leaver is presented. Application-specific-integrated-circuit (ASIC) implementation of this turbo decoder is carried out in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology node and its power consumption, design area and operating clock frequency are reported. Finally, a comparison with similar contributions in the literature has shown that the implemented turbo decoder achieves energy efficiency of 0.28 nJ/b/iteraions. Similarly, it has achieved a highest throughput of 28 Mbps among radix-2 and radix-4 non-parallel turbo decoders.

关键词： map algorithm Turbo code BER performance and ASIC design

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Effective Log-map Decoding for Low Complexity algorithm with Piecewise Linear and Scaling Factor

Effective Log-MAP Decoding for Low Complexity Algorithm with...

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2012 International Conference on Computer Science and Artificial Intelligence(CSAI 2012)

作者： Gang Bi Jianyi Wang Dept. of Information & Electronic Engineering Zhejiang University City College Dept. of Information Science & Electronic Engineering Zhejiang University

It is an issue that decoding performance of Max-Log-map algorithm is worse 0.5dB than that of Log-map algorithm while Log-map algorithm has the large complexity of decoding. This paper proposes to replace the Jacobian formula of Log-map algorithm with piecewise-linear term (PLT), and by studying the influence of the scaling factor on the decoding performance. We achieve the best way to optimize the performance of Turbo decoding. The research result show that when the number of segments is three and the scaling factor is 0.7, the decoding performance is slightly better than that of Log-map algorithm, and the computational complexity of the proposed algorithm has just one more multiplication and maximum than the Max-Log-map algorithm .

关键词： Turbo codes map algorithm AWGN channel iterative decoding scaling factor

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Effective Log-map Decoding for Low Complexity algorithm with Piecewise Linear and Scaling Factor

Effective Log-MAP Decoding for Low Complexity Algorithm with...

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2010 International Colloquium on Computing,Communication, Control, and Management (CCCM2010)

作者： Gang Bi~(1,2) 1.Dept.of Information & Electronic Engineering Zhejiang University City College Hangzhou,310015,China 2.Dept.of Information Science & Electronic Engineering Zhejiang University Hangzhou,310027,China Jianyi Wang Dept.of Information Science & Electronic Engineering Zhejiang University Hangzhou,310027,China

It is an issue that decoding performance of Max-Log-map algorithm is worse 0.5dB than that of Log-map algorithm while Log-map algorithm has the large complexity of decoding. This paper proposes to replace the Jacobian formula of Log-map algorithm with piecewise-linear term(PLT),and by studying the influence of the scaling factor on the decoding *** achieve the best way to optimize the performance of Turbo *** research result show that when the number of segments is three and the scaling factor is 0.7, the decoding performance is slightly better than that of Log-map algorithm,and the computational complexity of the proposed algorithm has just one more multiplication and maximum than the Max-Log-map algorithm.

关键词： Turbo codes map algorithm AWGN channel iterative decoding scaling factor

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VHDL implementation of a turbo decoder with log-map-based iterative decoding

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2004年第4期53卷 1268-1278页

作者： Tong, YH Yeap, TH Chouinard, JY Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada Univ Laval Dept Elect & Comp Engn Quebec City PQ G1K 7P4 Canada

Turbo code is one of the most significant achievements in coding theory during the last decade. By concatenating two simple convolutional codes in parallel, it has been shown that transmission systems employing turbo codes could offer near-capacity performance. More importantly, by employing a suboptimal iterative decoding structure with soft-in/soft-out (SISO) maximum a posteriori-probability (APP) decoding algorithm, the near-capacity performance is achievable at a feasible decoding complexity. Given the outstanding performance of turbo code, the challenge now is to implement it into various communication systems at affordable decoding complexity using current very large scale integration (VLSI) technologies. In this paper, we first investigated the existing four different turbo decoding algorithms. Comparisons of both their performances and implementation complexities were performed. Log-maximum a posteriori (map) -based turbo decoding was found to offer the best performance-complexity compromise. A register-transfer-level (RTL) 12-bit fixed-point turbo decoder based on Log-map algorithm was then designed and simulated using VHDL as the hardware description language. The implemented RTL model was verified by comparing its performances with those obtained from a C-language implementation of the same turbo decoder.

关键词： iterative decoding map algorithm soft-in/soft-out (SISO) decoder turbo code very large scale integration (VLSI) VHDL

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Performance evaluation for map state estimate fusion

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2004年第2期40卷 706-714页

作者： Chang, KC Tian, Z Mori, S Chong, CY George Mason Univ Dept SEOR Fairfax VA 22030 USA Michigan Technol Univ Dept Elect & Comp Engn Houghton MI 49931 USA ALPHATECH Inc San Diego CA 92121 USA

This paper presents a quantitative performance evaluation method for the maximum a posteriori (map) state estimate fusion algorithm. Under ideal conditions where data association is assumed to be perfect, it has been shown that the map or best linear unbiased estimate (BLUE) fusion formula provides the best linear minimum mean squared estimate (LMMSE) given local estimates under the linear Gaussian assumption for a static system. However, for a dynamic system where fusion is recursively performed by the fusion center on local estimates generated from local measurements, it is not obvious how the map algorithm will perform. In the past, several performance evaluation methods have been proposed for various fusion algorithms, including simple convex combination, cross-covariance combination, information matrix, and map fusion. However, not much has been done to quantify the steady state behavior of these fusion methods for a dynamic system. The goal of this work is to present analytical fusion performance results for map state estimate fusion without extensive Monte Carlo simulations, using an approach developed for steady state performance evaluation for track fusion. Two different communication strategies are considered: fusion with and without feedback to the sensors. Analytic curves for the steady state performance of the fusion algorithm for various communication patterns are presented under different operating conditions.

关键词： .fusion algorithm LMMSE local estimates linear Gaussian map algorithm map fusion steady state performance track fusion various communication sensor measurements

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VLSI architectural design tradeoffs for sliding-window Log-map decoders

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年第4期13卷 439-447页

作者： Wu, CM Shieh, MD Wu, CH Hwang, YT Chen, JH Natl Appl Res Labs CIC Hsinchu 300 Taiwan Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Natl Chung Cheng Univ Dept Elect Engn Chiayi 621 Taiwan Natl Yunlin Univ Sci & Technol Dept Elect Engn Yunlin 640 Taiwan

Turbo codes have received tremendous attention and have commenced their practical applications due to their excellent error-correcting capability. Investigation of efficient iterative decoder realizations is of particular interest because the underlying soft-input soft-output decoding algorithms usually lead to highly complicated implementation. This paper describes the architectural design and analysis of sliding-window (SW) Log-map decoders in terms of a set of predetermined parameters. The derived mathematical representations can be applied to construct a variety of VLSI architectures for different applications. Based on our development, a SW-Log-map decoder complying with the specification of third-generation mobile radio systems is realized to demonstrate the performance tradeoffs among latency, average decoding rate, area/computation complexity, and memory power consumption. This paper thus provides useful and general information on practical implementation of SW-Log-map decoders.

关键词： iterative decoding map algorithm sliding window algorithm turbo code VLSI architecture and design

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Reduced-state variant of optimum map equaliser

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ELECTRONICS LETTERS 1999年第19期35卷 1611-1612页

作者： Qian, XC Zhao, CM Cheng, SX Southeast Univ Natl Mobile Commun Res Lab Nanjing 210096 Peoples R China

Although the reduced-state technique has been widely used in Viterbi equalisers, its application to maximum a posteriori probability (map) equalisers is not satisfactory because it cannot operate due to the backward recursion of the conventional map algorithm. A new kind of map algorithm is proposed in which the forward and backward recursions are exactly symmetric. The reduced-state technique can thus be applied to both forward and backward recursions and a gain in performance is achieved over that of conventional reduced-state map equalisers at the cost of double the computational overhead.

关键词： forward recursion Communication channel equalisation and identification optimum map equaliser equalisers map algorithm AWGN channels Information theory Other topics in statistics probability maximum a posteriori probability equalisers backward recursion reduced-state variant

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Matrix approach for fast implementations of logarithmic map decoding of turbo codes

Matrix approach for fast implementations of logarithmic MAP ...

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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 2001)

作者： Wang, DY Kobayashi, H Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0780370805

This paper describes two new matrix transform algorithms for the Max-Log-map decoding of turbo codes. In the proposed algorithms, the successive decoding procedures carried out in the conventional Max-Log-map algorithm are performed in parallel, and well formulated into a set of simple and regular matrix operations, which can therefore considerably speed up the decoding operations and reduce the computational complexity. The matrix Max-Log-map algorithms also maintain the advantage of the general logarithmic map like algorithms in avoiding complex numerical representation problems. They particularly facilitate the implementations of the logarithmic map like algorithms in special-purpose parallel processing VLSI hardware architectures. The matrix algorithms also allow simple implementations by using shift registers. The proposed implementation architectures for the matrix Max-Log-map decoding can effectively reduce the memory capacity and simplify the data accesses and transfers required by the conventional Max-Log-map as well as map algorithms.

关键词： turbo codes map algorithm Max-Log-map algorithm matrix transform VLSI

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