In this paper, we propose a joint decoding scheme called AC-map decoder for multiple input single output (MISO) wireless cooperative communication network that consists of single source, single relay, and single desti...
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In this paper, we propose a joint decoding scheme called AC-map decoder for multiple input single output (MISO) wireless cooperative communication network that consists of single source, single relay, and single destination. The proposed scheme is based on both Alamouti combining (AC) scheme and maximum a posteriori (map) decoder and is used to estimate the data at the destination. The AC-map decoder is optimal in the sense that it minimizes the end-to-end bit error rate (BER). In order to analyze performance of the proposed decoder, we derive a closed form expression for the upper bound (UB) on the end-to-end error probability. Distances between system nodes, transmit energy, and channel noise and fading effects are considered in the derivation of the UB. Numerical results show that the closed form UB is very tight and it almost coincides with the exact BER results obtained from simulations. Therefore, we use the derived UB expression to study the effects of the relay position on the BER performance and to find the optimal location of the relay node.
A modified map decoder architecture to reduce the power using folded technique is presented in this article. Firstly, the folded technique is applied in the interleaving and deinterleaving unit and then in the map dec...
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A modified map decoder architecture to reduce the power using folded technique is presented in this article. Firstly, the folded technique is applied in the interleaving and deinterleaving unit and then in the map decoder unit. The number of latches is reduced by using folded technique in the interleaving and deinterleaving unit. Here the end-to-end delay by using the proposed folded technique in the interleaving block is 2M. But existing reports reveal that end-to-end delay is 2MN-2M+2 for BI and M(N-1) for FCI. In addition to the end-to-end delay, the number of latches is also reduced by using folded technique. We have used only M-2 latches, whereas for other methods the number of latches utilised is more. The proposed map decoder reduce the memory elements up to 88% for the block interleaver, when M=NJ. In addition to that we achieved a memory element of 2 (K) (-1)+4 when calculating LLR by applying folded technique in the map decoder. Total power consumption is 160.3mW when folded technique is used in the interleaving block and the map decoder section. This ratio is less than the existing reported values for K=5, code rate 1/2 and k=4.
In this paper we present a parallel implementation of a map decoder for synchronization error correcting codes. For a modest implementation effort, we demonstrate a considerable decoding speedup, up to two orders of m...
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In this paper we present a parallel implementation of a map decoder for synchronization error correcting codes. For a modest implementation effort, we demonstrate a considerable decoding speedup, up to two orders of magnitude even on consumer GPUs. This enables the analysis of much larger codes and worse channel conditions than previously possible, and makes applications of such codes feasible for software implementations.
Maximum a posteriori probability (map) decoder is an integral part of the most exciting error correcting turbo decoders. A high speed architecture for map decoder is an essential entity for the design of high throughp...
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ISBN:
(纸本)9780769548890
Maximum a posteriori probability (map) decoder is an integral part of the most exciting error correcting turbo decoders. A high speed architecture for map decoder is an essential entity for the design of high throughput turbo decoder which is widely used in the recent wireless communication standards. In this paper, a new sliding window approach for the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm used in the design of map decoder is presented. An architecture for map decoder based on this approach and its operation is also included in this paper. The proposed map decoder architecture is implemented on field programmable gate array (FPGA) and the results are discussed. The proposed map decoder operates at a maximum frequency of 346 MHz and is compared with the state of the art implementations of map decoder. Finally, the bit error rate (BER) performance of an implemented map decoder in a communication environment is measured.
In this paper, we develop a new capacityapproaching code, namely, parallel-concatenated (PC)-Low Density Parity Check (LDPC) convolutional code that is based on the parallel concatenation of trellis-based quasi-cyclic...
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In this paper, we develop a new capacityapproaching code, namely, parallel-concatenated (PC)-Low Density Parity Check (LDPC) convolutional code that is based on the parallel concatenation of trellis-based quasi-cyclic LDPC (TQCLDPC) convolutional codes. The proposed PC-LDPC convolutional code can be derived from any QC-LDPC block code by introducing the trellis-based convolutional dependency to the code. The capacity-approaching PC-LDPC convolutional codes are encoded through parallel concatenated trellis-based QC recursive systematic convolutional (RSC) encoder (namely, QCRSC encoder) that is also proposed in this paper. The proposed PC-LDPC convolutional code and the associated encoder retain a fine input granularity on the order of the lifting factor of the underlying block code. We also describe the corresponding trellisbased QC maximum a posteriori probability (namely, QC-map) decoder that efficiently decodes the PC-LDPC convolutional code. Performance and hardware implementation results show that the PC-LDPC convolutional codes with the QC-map decoder have two times lower complexity for a given bit-error-rate (BER), signal-to-noise ratio, and data rate, than conventional QC-LDPC block codes and LDPC convolutional codes. Moreover, the PC-LDPC convolutional code with the QC-map decoder outperforms the conventional QC-LDPC block codes by more than 0.5 dB for a given BER, complexity, and data rate and approaches Shannon capacity limit with a gap smaller than 1.25 dB. This low decoding complexity and the fine granularity make it feasible to efficiently implement the proposed capacityapproaching PC-LDPC convolutional code and the associated trellis-based QC-map decoder in next generation ultra-high data rate mobile systems.
The maximum a posterior (map) decoding scheme is presented here for cooperative communication networks that adopt the parity forwarding as a cooperation protocol. The map decoder is optimal in the sense that it minimi...
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The maximum a posterior (map) decoding scheme is presented here for cooperative communication networks that adopt the parity forwarding as a cooperation protocol. The map decoder is optimal in the sense that it minimises the error probability. The authors consider a wireless network that is composed of two sources: two relays and a single destination. A closed-form expression is derived for upper bound on the bit error probability. The complexity of derivation comes from the fact that although the source generates data with equal probability, the data received at the destination does not have the same a priori probability. That is because of the error that occurs in the source-to-relay link. Therefore, the map decoding rule cannot be simplified to the maximum likelihood decoding rule. The results show that the analytical upper bound is very tight and almost coincides with the exact error probability obtained from simulations at higher values of the signal-to-noise ratio. Accordingly, the closed-form expression of the upper bound can be used to fully study and understand the diversity performance of the system.
A modified architecture for minimised power consumption in the maximum a posteriori (map) decoder based on retiming for register minimisation is proposed in this study. Retiming for register minimisation technique is ...
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A modified architecture for minimised power consumption in the maximum a posteriori (map) decoder based on retiming for register minimisation is proposed in this study. Retiming for register minimisation technique is introduced in the trellis unit of the map decoder. Forward state metric and reverse state metric values are retained till the end of the time scale (k -1)' to calculate log-likelihood ratio (LLR) value. By applying this technique, the number of registers gets reduced, where the node has several output edges carrying the same signal. Depending on the time scale, memory latches reduces from k[(k - 1)/2] to (k- 1)' in the LLR unit of map decoder. Using this technique, optimised architecture is derived and the authors have achieved the power consumption of 173.2 mW, which is less than 12.21% with the reported values, for K = 5, code rate 1/2 and time scale k = 4. When forward flip-flop retiming is applied 6.08% clock frequency increased and 5.53% total time delay reduced as compared with the register retiming technique.
An FPGA implementation of a highly parallel and configurable architecture for turbo decoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for soft...
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ISBN:
(纸本)9781479920785
An FPGA implementation of a highly parallel and configurable architecture for turbo decoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for software defined radio applications. A novel combination of the next iteration initialization method and the parallel and sliding window techniques is used in the map algorithm. This allows high throughput and reduced storage requirements, as compared to other solutions. Synthesis results on Altera FPGAs show that this architecture can reach 337.6 Mbps at 8 decoding iterations.
Mobile adhoc network (MANET) refers to an arrangement of wireless mobile nodes that have the tendency of dynamically and freely self-organizing into temporary and arbitrary network topologies. Orthogonal frequency div...
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Mobile adhoc network (MANET) refers to an arrangement of wireless mobile nodes that have the tendency of dynamically and freely self-organizing into temporary and arbitrary network topologies. Orthogonal frequency division multiplexing (OFDM) is the foremost choice for MANET system designers at the Physical Layer due to its inherent property of high data rate transmission that corresponds to its lofty spectrum efficiency. The downside of OFDM includes its sensitivity to synchronization errors (frequency offsets and symbol time). Most of the present day techniques employing OFDM for data transmission support mobility as one of the primary features. This mobility causes small frequency offsets due to the production of Doppler frequencies. It results in intercarrier interference (ICI) which degrades the signal quality due to a crosstalk between the subcarriers of OFDM symbol. An efficient frequency-domain block-type pilot-assisted ICI mitigation scheme is proposed in this article which nullifies the effect of channel frequency offsets from the received OFDM symbols. Second problem addressed in this article is the noise effect induced by different sources into the received symbol increasing its bit error rate and making it unsuitable for many applications. Forward-error-correcting turbo codes have been employed into the proposed model which adds redundant bits into the system which are later used for error detection and correction purpose. At the receiver end, maximum a posteriori (map) decoding algorithm is implemented using two component map decoders. These decoders tend to exchange interleaved extrinsic soft information among each other in the form of log likelihood ratio improving the previous estimate regarding the decoded bit in each iteration.
We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/...
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We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several map decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm(2) and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 map decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations (C) 2010 Elsevier B.V. All rights reserved.
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