检索结果-内蒙古大学图书馆

IEEE International Conference on Signal Processing, Computing and Control (ISPCC)

作者： Shrestha, Rahul Paily, Roy Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati 781039 Assam India

ISBN: (纸本)9781467361880;9781467361903

In this paper, a systematic approach of hardware prototyping and testing a digital design of maximum-a-posteriori (map) decoder for a communication system is presented. A map decoder architecture for the high speed application is chosen for the implementation on field-programmable-gate-array (FPGA) board. The test-setup of a communication system with binary-phase-shift-keying (BPSK) modulation scheme in an additive-white-Gaussian-noise (AWGN) channel environment is designed to verify the hardware prototype of the decoder. Subsequently, the integration of hardware prototype with integrated logic analyzer core using control cores and parallel cables are presented. The hardware prototype of map decoder implemented on FPGA has achieved a biterror-rate (BER) of 10(-4) at an E-b/N-0 of 4.75 dB and has a degraded performance as compared to simulated map algorithm by approximately 0.2 dB. In addition, the implemented map decoder has a maximum achievable frequency of 411 MHz.

关键词： map algorithm FPGA BER performance communication system and VLSI system design

来源：评论

学校读者我要写书评

暂无评论

Real-time Implementation of Maximum a Posteriori (map) Based Noise Reductions Using Leon 3 System on Chip 1

Real-time Implementation of Maximum a Posteriori (MAP) Based...

引用

International Conference on Electrical Engineering and Computer Science (ICEECS)

作者： Santriaji, Muhammad H. Mauludin, Hilman Surgawiwaha, Dian Adiono, Trio Inst Teknol Bandung Bandung Indonesia

ISBN: (纸本)9781479984787

Maximum a Posteriori (map) is an advance method to estimate noise for various audio noise reduction applications. map algorithm with variable speech distribution involves complex and intensive computation. Implementation in naive method can't achieve real-time constraint. This paper proposed a method to optimize the map algorithm with variable speech distribution in software implementation for System on Chip (SoC). System utilizes Leon 3 microprocessor as main processing system. System is implemented in software hardware co-design to ensure flexibility and reduce computational time burden. Optimization has been done by replacing some arithmetic function with approximation function and by giving optimization option in the compiler. The simulation results show that the optimized map algorithm produces a linear result in SNR enhancement and faster computation time under time budget constraint.

关键词： map algorithm Variable Speech Distribution Noise Reduction System System on Chip Hardware Software Co-design

来源：评论

学校读者我要写书评

暂无评论

Parallel vlsi architecture for map turbo decoder

Parallel vlsi architecture for map turbo decoder

引用

13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications

作者： Dobkin, R Peleg, M Ginosar, R Technion Israel Inst Technol Dept Elect Engn IL-32000 Haifa Israel

ISBN: (纸本)0780375890

Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires large memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. Latency is reduced up to twenty times and throughput for large blocks is increased up to five-fold relative to sequential decoders, using the same area of silicon, and achieving the same coding gain. The parallel architecture scales favourably - latency and throughput improve with growing block size and chip area.

关键词： map algorithm turbo codes parallel architectures decoders interleaver

来源：评论

学校读者我要写书评

暂无评论

Finite Wordlength Analysis and Adaptive Decoding for Turbo/map Decoders

引用

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 2001年第3期29卷 209-221页

作者： Wang, Zhongfeng Suzuki, Hiroshi Parhi, Keshab K. Dept. of Elec. and Comp. Engineering University of Minnesota Minneapolis MN United States Kawasaki Steel Corporation LSI Division Chiba Japan Morphics Technology Inc. Campbell CA 95008 675 Campbell Tech. PKWY United States Tsinghua University Beijing China Beijing Huahai New Technol. D. Beijing China Morphics Technology Inc. Campbell CA United States Kyoto University Kyoto Japan Department of Electrical Engineering University of Minnesota Minneapolis MN United States Broadcom Corporation Irvine CA United States McKnight University Dept. of Elec. and Comp. Engineering University of Minnesota Minneapolis MN United States Indian Institute of Technology Kharagpur India University of Pennsylvania Philadelphia PA United States University of California Berkeley CA United States

Turbo decoders inherently require large hardware for VLSI implementation as a large amount of memory is required to store incoming data and intermediate computation results. Design of highly efficient Turbo decoders requires reduction of hardware size and power consumption. In this paper, finite precision effects on the performance of Turbo decoders are analyzed and the optimal word lengths of variables are determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for Turbo decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose a novel adaptive decoding approach which does not lead to performance degradation and is suitable for VLSI implementation.

关键词： Adaptive decoding map algorithm Turbo codes VLSI implementation

来源：评论

学校读者我要写书评

暂无评论

A 400Mb/s Radix-4 map decoder with fast recursion architecture

A 400Mb/s Radix-4 MAP decoder with fast recursion architectu...

引用

10th International Conference on Advanced Communication Technology

作者： Zhang, Cheng Wang, Xuejing Ye, Fan Ren, Junyan Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9788955191356

Turbo decoder's throughput is highly restricted by the recursion architecture of map decoder. In this paper, a new architecture of map decoder is presented. We improve the recursion architecture of the traditional Radix-4 map decoder in order to gain higher throughput, meanwhile the modification could reduce the coding gain loss caused by the approximation of the traditional architecture. A new data flow of the Radix-4 map decoder is also adopted to reduce the memory access. The proposed architecture could increase The throughput by 21%, while its hardware complexity increase is negligible.

关键词： error-correcting code turbo code map algorithm high throughput

来源：评论

学校读者我要写书评

暂无评论

Punctured turbo codes for bandwidth-efficient transmission

引用

DEFENCE SCIENCE JOURNAL 2006年第4期56卷 585-590页

作者： Rekh, Shobha Rani, S. Subha Shanmugam, A. Joshua, John Kulothungan PSG Coll Technol Coimbatore Tamil Nadu India Karunya Deemed Univ Coimbatore 641028 Tamil Nadu India Bannari Amman Inst Technol Coimbatore Tamil Nadu India

Turbo codes are the error-coding schemes applied nowadays in wireless networks. In naval applications, the information is mostly sent through wireless networks and the data is more prone to noise. Since very important data has to be communicated, it is necessary to get back the original data in the receiver. In military applications also, the soldiers wear electronic jackets which are connected by wireless networks. In such applications, the data loss is not affordable and - there is also a need to utilise the bandwidth efficiently through puncturing by means of which certain bits are deleted before transmission from the output of encoder. By,means of this punctured turbo codes, bandwidth-efficient coding is achieved. Hence, it is necessary to design turbo codes with an efficient puncturing pattern so that the performance of the punctured code is also improved in spite of deletion of few bits before transmission. This paper deals in choosing the puncturing patterns that lead to systematic rate-compatible punctured turbo codes (RCPTCs) which also give a reduction in bit-error rate. ' The design criterion for choosing the best puncturing patterns is based on the minimum weight of code words and their multiplicities. The best puncturing pattern chosen is tested for its performance by simulating turbo codes for an additive white Gaussian noise (AWGN) channel. Compared with the existing puncturing pattern;the pattern proposed is able to achieve a gain of 0.5 dB at a bit-error rate of 10(-3).

关键词： wireless transmission turbo codes error-coding schemes rate-compatible punctured turbo codes additive white Gaussian noise map algorithm soft output viterbi algorithm RCPC rate-compatible punctured codes recursive systematic convolutional encoders

来源：评论

学校读者我要写书评

暂无评论

A soft-output decoding algorithm for concatenated systems

引用

IEEE TRANSACTIONS ON INFORMATION THEORY 1996年第2期42卷 543-553页

作者： Wang, XA Wicker, SB School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

In order to fully utilize the SDD (soft-decision decoding) capacity of the outer codes in a concatenated system, reliability information on the inner decoder outputs (called soft outputs) needs to be provided to the outer decoder, This paper shows that a modified map algorithm can be effectively and accurately used to generate such information, In the course of the presentation, a metric based on the reliability information is proposed for the outer decoder, This metric has the Euclidean metric on AWGN channels as its special case, which leads to the concept of generalized SDD (GSDD), Several practical concerns regarding the proposed soft-output decoder are addressed through theoretical analysis and simulation: the effect of finite decoding depth, computational complexity, range overflow, and scaling, Comparisons to previous work on soft-output decoders are made.

关键词： soft outputs concatenated codes map algorithm SOVA generalized soft decision decoding

来源：评论

学校读者我要写书评

暂无评论

Multi-dimensional turbo codes: Performance and simplified decoding structure

引用

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1997年第11期E80A卷 2089-2094页

作者： Li, JF Imai, H Institute of Industrial Science University of Tokyo Tokyo 106 Japan

Turbo codes have fascinated many coding researchers because of their near-Shannon-limit error correction performance. In this paper, we discuss multi-dimensional turbo codes which are parallel concatenation of multiple constituent codes. The average upper bound to bit error probability of multidimensional turbo codes is derived. The bound shows that the interleaver gains of this kind of codes are larger than that of conventional two-dimensional turbo codes. Simplified structures of multi-dimensional turbo encoder and decoder are proposed for easier implementation. Simulation results show that for a given interleaver size, by increasing the dimension, great performance improvement can be obtained.

关键词： multi-dimensional turbo code iterative decoding map algorithm interleaver

来源：评论

学校读者我要写书评

暂无评论

Neural network implementation of the BCJR algorithm

引用

DIGITAL SIGNAL PROCESSING 2007年第1期17卷 353-359页

作者： Sazli, Murat Husnu Isik, Can Ankara Univ Fac Engn Dept Elect Engn TR-06100 Ankara Turkey Syracuse Univ LC Smith Coll Engn & Comp Sci Dept Elect Engn Syracuse NY 13244 USA

In this paper, we first show that the BCJR algorithm (or Bahl algorithm) can be implemented via some matrix manipulations. As a direct result of this, we also show that this algorithm is equivalent to a feedforward neural network structure. We verified through computer simulations that this novel neural network implementation yields identical results with the BOR algorithm. (c) 2006 Elsevier Inc. All rights reserved.

关键词： turbo codes turbo coding/decoding channel coding Bahl algorithm BCJR algorithm map algorithm neural networks

来源：评论

学校读者我要写书评

暂无评论

Partial turbo detection with reduced complexity

引用

INTERNATIONAL JOURNAL OF ELECTRONICS 2011年第6期98卷 825-831页

作者： Ouardi, Aissa Djebbari, A. Bouazza, B. S. Univ Djillali Liabes Sidi Bel Abbes Telecommun & Digital Signal Proc Lab Dept Elect Sidi Bel Abbes 22000 Algeria

In this article, we propose a novel method for reducing the complexity of the turbo detector map (maximum a posteriori). The basic idea consists in turbo detecting a part of intersymbol interference (ISI) after decomposing the channel in two parts. We show that we can reduce the trellis complexity in the turbo process at a certain cost, i.e. performance loss.

关键词： turbo detection complexity reduction intersymbol interference (ISI) map algorithm interference canceller (IC) partial turbo detection channel decomposition

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：