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An intuitive justification and a simplified implementation of the map decoder for convolutional codes

IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 1998年第2期16卷 260-264页

作者： Viterbi, AJ Qualcomm Inc San Diego CA 92121 USA

An intuitive shortcut to understanding the maximum a posteriori (map) decoder is presented based on era approximation. This is shown to correspond to a dual-maxima computation combined with forward and backward recursions of Viterbi algorithm computations, The logarithmic version of the map algorithm can similarly be reduced to the same form by applying the same approximation, Conversely, if a correction term is added to the approximation, the exact map algorithm is recovered, It is also shown how the map decoder memory can be drastically reduced at the cost of a modest increase in processing speed.

关键词： dual-maxima map decoder soft-decision metric Viterbi algorithm

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A GPU Implementation of a map decoder for Synchronization Error Correcting Codes

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IEEE COMMUNICATIONS LETTERS 2013年第5期17卷 996-999页

作者： Briffa, Johann A. Univ Surrey Dept Comp Guildford GU2 7XH Surrey England

In this paper we present a parallel implementation of a map decoder for synchronization error correcting codes. For a modest implementation effort, we demonstrate a considerable decoding speedup, up to two orders of magnitude even on consumer GPUs. This enables the analysis of much larger codes and worse channel conditions than previously possible, and makes applications of such codes feasible for software implementations.

关键词： Insertion-deletion correction map decoder forward-backward algorithm CUDA GPU

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Design and Implementation of a High Speed map decoder Architecture for Turbo Decoding

Design and Implementation of a High Speed MAP Decoder Archit...

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26th International Conference on VLSI Design Held Concurrently with 12th International Conference on Embedded Systems Design

作者： Shrestha, Rahul Paily, Roy Indian Inst Technol Dept Elect & Elect Engn Gauhati 781039 Assam India

ISBN: (纸本)9780769548890

Maximum a posteriori probability (map) decoder is an integral part of the most exciting error correcting turbo decoders. A high speed architecture for map decoder is an essential entity for the design of high throughput turbo decoder which is widely used in the recent wireless communication standards. In this paper, a new sliding window approach for the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm used in the design of map decoder is presented. An architecture for map decoder based on this approach and its operation is also included in this paper. The proposed map decoder architecture is implemented on field programmable gate array (FPGA) and the results are discussed. The proposed map decoder operates at a maximum frequency of 346 MHz and is compared with the state of the art implementations of map decoder. Finally, the bit error rate (BER) performance of an implemented map decoder in a communication environment is measured.

关键词： BCJR algorithm turbo code map decoder sliding window technique FPGA and BER performance

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A modified map decoder architecture for low power consumption using folded technique

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INTERNATIONAL JOURNAL OF ELECTRONICS 2013年第7期100卷 900-912页

作者： Shiyamala, S. Rajamani, V. Sri Subramanya Coll Engn & Technol Dept Elect & Commun Engn Palani TN India Indra Ganesan Coll Engn Dept Elect & Commun Engn Tiruchirappalli TN India

A modified map decoder architecture to reduce the power using folded technique is presented in this article. Firstly, the folded technique is applied in the interleaving and deinterleaving unit and then in the map decoder unit. The number of latches is reduced by using folded technique in the interleaving and deinterleaving unit. Here the end-to-end delay by using the proposed folded technique in the interleaving block is 2M. But existing reports reveal that end-to-end delay is 2MN-2M+2 for BI and M(N-1) for FCI. In addition to the end-to-end delay, the number of latches is also reduced by using folded technique. We have used only M-2 latches, whereas for other methods the number of latches utilised is more. The proposed map decoder reduce the memory elements up to 88% for the block interleaver, when M=NJ. In addition to that we achieved a memory element of 2 (K) (-1)+4 when calculating LLR by applying folded technique in the map decoder. Total power consumption is 160.3mW when folded technique is used in the interleaving block and the map decoder section. This ratio is less than the existing reported values for K=5, code rate 1/2 and k=4.

关键词： map decoder convolutional interleaving folded technique end-to-end delay power consumption

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A memory-efficient block-wise map decoder architecture

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ETRI JOURNAL 2004年第6期26卷 615-621页

作者： Kim, S Hwang, SY Kang, MJ Sogang Univ Dept Elect Engn Seoul 121742 South Korea Pinetron Co Ltd Seoul South Korea

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (map) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise map decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous NILAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

关键词： map decoder training length memory requirement

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Decoding scheme for relay networks with parity forwarding cooperation protocol

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IET COMMUNICATIONS 2014年第8期8卷 1317-1324页

作者： Khalaf, Taha A. Ramzy, Safwat M. Assiut Univ Dept Elect Engn Assiut 71516 Egypt Sohag Univ Dept Elect Engn Sohag Egypt

The maximum a posterior (map) decoding scheme is presented here for cooperative communication networks that adopt the parity forwarding as a cooperation protocol. The map decoder is optimal in the sense that it minimises the error probability. The authors consider a wireless network that is composed of two sources: two relays and a single destination. A closed-form expression is derived for upper bound on the bit error probability. The complexity of derivation comes from the fact that although the source generates data with equal probability, the data received at the destination does not have the same a priori probability. That is because of the error that occurs in the source-to-relay link. Therefore, the map decoding rule cannot be simplified to the maximum likelihood decoding rule. The results show that the analytical upper bound is very tight and almost coincides with the exact error probability obtained from simulations at higher values of the signal-to-noise ratio. Accordingly, the closed-form expression of the upper bound can be used to fully study and understand the diversity performance of the system.

关键词： relay networks (telecommunication) cooperative communication maximum likelihood decoding error statistics relay networks parity forwarding cooperation protocol maximum a posterior decoding scheme cooperative communication networks map decoder wireless network closed-form expression bit error probability equal probability source-to-relay link maximum likelihood decoding rule

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Bit error rate performance analysis of AC-map in multiple input single output wireless relay network

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EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING 2020年第1期2020卷 1-13页

作者： Khalaf, Taha A. Mohammed, Hazem Univ Tabuk Dept Elect Engn Tabuk 71491 Saudi Arabia Assiut Univ Dept Elect Engn Assiut 71516 Egypt

In this paper, we propose a joint decoding scheme called AC-map decoder for multiple input single output (MISO) wireless cooperative communication network that consists of single source, single relay, and single destination. The proposed scheme is based on both Alamouti combining (AC) scheme and maximum a posteriori (map) decoder and is used to estimate the data at the destination. The AC-map decoder is optimal in the sense that it minimizes the end-to-end bit error rate (BER). In order to analyze performance of the proposed decoder, we derive a closed form expression for the upper bound (UB) on the end-to-end error probability. Distances between system nodes, transmit energy, and channel noise and fading effects are considered in the derivation of the UB. Numerical results show that the closed form UB is very tight and it almost coincides with the exact BER results obtained from simulations. Therefore, we use the derived UB expression to study the effects of the relay position on the BER performance and to find the optimal location of the relay node.

关键词： MISO relay network map decoder BER Upper bound

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Low Complexity Soft decoder for Nordstrom-Robinson Code With Application to the Chinese DTTB Standard

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IEEE TRANSACTIONS ON BROADCASTING 2009年第3期55卷 668-673页

作者： Xie, Qiuliang Peng, Kewu Wang, Jun Song, Jian Wang, Jintao Yang, Zhixing Tsinghua Univ Tsinghua Natl Lab Informat Sci & Technol Dept Elect Engn Beijing 100084 Peoples R China

Nordstrom-Robinson (NR) code followed by 4 quadrature-amplitude modulation (4QAM) mapping is one of the working modes in the Chinese digital television terrestrial broadcasting (DTTB) standard, where the outer code is a low-density parity-check (LDPC) code. Since LDPC decoders usually accept soft rather than hard inputs for better error performance, soft NR decoders are highly recommended. In this paper, several novel low-complexity soft NR decoders are proposed with excellent error performance. Simulation results show that the proposed algorithm based on the maximum, second and third maximum (MST) cross correlation values achieves very low complexity at the cost of performance loss only about 0.1 dB at bit error rate (BER) of 10(-6), under both additive white Gaussian noise (AWGN) and independent Rayleigh fading channels, compared to the ideal maximum a posteriori (map) decoder.

关键词： DTMB LDPC decoder map decoder Nordstrom-Robinson (NR) code

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Performance enhancement of wireless mobile adhoc networks through improved error correction and ICI cancellation

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EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING 2012年第1期2012卷 1页

作者： Sabir, Zeeshan Babar, M. Inayatullah Shah, Syed Waqar Univ Engn & Technol Peshawar Pakistan

Mobile adhoc network (MANET) refers to an arrangement of wireless mobile nodes that have the tendency of dynamically and freely self-organizing into temporary and arbitrary network topologies. Orthogonal frequency division multiplexing (OFDM) is the foremost choice for MANET system designers at the Physical Layer due to its inherent property of high data rate transmission that corresponds to its lofty spectrum efficiency. The downside of OFDM includes its sensitivity to synchronization errors (frequency offsets and symbol time). Most of the present day techniques employing OFDM for data transmission support mobility as one of the primary features. This mobility causes small frequency offsets due to the production of Doppler frequencies. It results in intercarrier interference (ICI) which degrades the signal quality due to a crosstalk between the subcarriers of OFDM symbol. An efficient frequency-domain block-type pilot-assisted ICI mitigation scheme is proposed in this article which nullifies the effect of channel frequency offsets from the received OFDM symbols. Second problem addressed in this article is the noise effect induced by different sources into the received symbol increasing its bit error rate and making it unsuitable for many applications. Forward-error-correcting turbo codes have been employed into the proposed model which adds redundant bits into the system which are later used for error detection and correction purpose. At the receiver end, maximum a posteriori (map) decoding algorithm is implemented using two component map decoders. These decoders tend to exchange interleaved extrinsic soft information among each other in the form of log likelihood ratio improving the previous estimate regarding the decoded bit in each iteration.

关键词： MANET OFDM Channel equalization Intercarrier interference (ICI) PCCC encoder map decoder Channel estimation Turbo codes

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Modified maximum a posteriori decoder architecture for low-power consumption

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IET SIGNAL PROCESSING 2013年第7期7卷 542-548页

作者： Subramani, Shiyamala Vayanaperumal, Rajamani Sri Subramanya Coll Engn & Technol Dept Elect & Commun Engn Palani Tamilnadu India Indra Ganesan Coll Engn Dept Elect & Commun Engn Tiruchirappalli Tamilnadu India

A modified architecture for minimised power consumption in the maximum a posteriori (map) decoder based on retiming for register minimisation is proposed in this study. Retiming for register minimisation technique is introduced in the trellis unit of the map decoder. Forward state metric and reverse state metric values are retained till the end of the time scale (k -1)' to calculate log-likelihood ratio (LLR) value. By applying this technique, the number of registers gets reduced, where the node has several output edges carrying the same signal. Depending on the time scale, memory latches reduces from k[(k - 1)/2] to (k- 1)' in the LLR unit of map decoder. Using this technique, optimised architecture is derived and the authors have achieved the power consumption of 173.2 mW, which is less than 12.21% with the reported values, for K = 5, code rate 1/2 and time scale k = 4. When forward flip-flop retiming is applied 6.08% clock frequency increased and 5.53% total time delay reduced as compared with the register retiming technique.

关键词： energy consumption flip-flops maximum likelihood decoding minimisation low-power consumption maximum a posteriori decoder architecture register minimisation technique map decoder forward state metric value reverse state metric value log-likelihood ratio value memory latches LLR unit clock frequency

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