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Robust video transmission over error-prone channels via error correcting arithmetic codes

IEEE COMMUNICATIONS LETTERS 2003年第12期7卷 596-598页

作者： Grangetto, M Magli, E Olmo, G Politecn Torino Dipartimento Elettron CERCOM I-10129 Turin Italy

We propose arithmetic codes (ACs) with a forbidden symbol as a joint entropy coding and error protection tool for robust video transmission over error-prone channels. In particular, we introduce a map decoder of ACs, and apply it to the transmission of 3-D SPIHT coded video and RTP/UDP/IP H.264 video with data partitioning. Experimental results show that the proposed system exhibits several advantages with respect to other schemes, and outperforms rate-compatible punctured convolutional (RCPC) codes in the applications considered.

关键词： .error protection motion vectors RCPC map decoder map DECODING Robust Video Transmission Error-Prone Channels Arithmetic Codes

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Capacity-Approaching TQC-LDPC Convolutional Codes Enabling Power-Efficient decoders

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IEEE TRANSACTIONS ON COMMUNICATIONS 2017年第1期65卷 1-13页

作者： Pisek, Eran Rajan, Dinesh Abu-Surra, Shadi Cleveland, Joseph R. PHAZR Inc Allen TX 75002 USA Southern Methodist Univ Dallas TX 75205 USA

In this paper, we develop a new capacityapproaching code, namely, parallel-concatenated (PC)-Low Density Parity Check (LDPC) convolutional code that is based on the parallel concatenation of trellis-based quasi-cyclic LDPC (TQCLDPC) convolutional codes. The proposed PC-LDPC convolutional code can be derived from any QC-LDPC block code by introducing the trellis-based convolutional dependency to the code. The capacity-approaching PC-LDPC convolutional codes are encoded through parallel concatenated trellis-based QC recursive systematic convolutional (RSC) encoder (namely, QCRSC encoder) that is also proposed in this paper. The proposed PC-LDPC convolutional code and the associated encoder retain a fine input granularity on the order of the lifting factor of the underlying block code. We also describe the corresponding trellisbased QC maximum a posteriori probability (namely, QC-map) decoder that efficiently decodes the PC-LDPC convolutional code. Performance and hardware implementation results show that the PC-LDPC convolutional codes with the QC-map decoder have two times lower complexity for a given bit-error-rate (BER), signal-to-noise ratio, and data rate, than conventional QC-LDPC block codes and LDPC convolutional codes. Moreover, the PC-LDPC convolutional code with the QC-map decoder outperforms the conventional QC-LDPC block codes by more than 0.5 dB for a given BER, complexity, and data rate and approaches Shannon capacity limit with a gap smaller than 1.25 dB. This low decoding complexity and the fine granularity make it feasible to efficiently implement the proposed capacityapproaching PC-LDPC convolutional code and the associated trellis-based QC-map decoder in next generation ultra-high data rate mobile systems.

关键词： LDPC convolutional code spatially-coupled LDPC decoder complexity IEEE802.11ad map decoder

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Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

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INTEGRATION-THE VLSI JOURNAL 2011年第4期44卷 305-315页

作者： Sun, Yang Cavallaro, Joseph R. Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high-throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several map decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm(2) and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 map decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations (C) 2010 Elsevier B.V. All rights reserved.

关键词： QPP interleaver Quadratic permutation polynomial Turbo decoder map decoder VLSI ASIC 3GPP LTE

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map Decoding with Random Interleaver for MPEG-4 Image Indoor Wireless Transmission System

MAP Decoding with Random Interleaver for MPEG-4 Image Indoor...

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14th Asia-Pacific Conference on Communications

作者： Mahapakulchai, Srijidtra Sapasirisopon, Itsaree Kasetsart Univ Dept Elect Engn Bangkok Thailand

ISBN: (纸本)9784885522321

Here, the investigation of the performance of map decoding with random interleaver for MPEG-4 image transmission system is described and analyzed. The performance evaluation is shown by setting map decoder to match the priori statistic of zerotree symbol sequence of the "Lena'' image. In this work, we successfully reduce the computation of the random interleaver process by omitting the calculation of the interleaving matrix P. In some cases, despite the computational reduction, the slight improvement of about 0.5-1 dB in PSNR can still be obtained.

关键词： map decoder Random interleaver Ring convolutional codes Rician fading channels

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EXIT functions for binary memoryless symmetric channels

EXIT functions for binary memoryless symmetric channels

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IEEE International Symposium on Information Theory

作者： Sharon, E Ashikhmin, A Litsyn, S Tel Aviv Univ Dept Elect Engn IL-69978 Tel Aviv Israel

ISBN: (纸本)0780382803

Use of Extrinsic Information Transfer (EXIT) functions characterizing mutual information between the input and output of constituent decoders significantly facilitates performance analysis of iterative decoding schemes. Previously EXIT functions derived for Binary Erasure Channel (BEC) were used as an approximation for other Binary Memoryless Symmetric (BMS) Channels. Here we improve on this approach by introducing a more accurate method to compute EXIT functions of some block codes for BMS channels. A general expression is derived for the Extrinsic Mutual Information at the output of map decoder. Using this expression we are able to compute EXIT functions for single parity-check codes over all BMS channels. Application of this result to analysis of convergence thresholds of LDPC codes is described. Using an alternative decoder coinciding with map decoder over BEC, we derive an expression for EXIT function over BEC, and based on it approximation to the EXIT function over AWGN channel for some block codes.

关键词： iterative decoding memoryless systems block codes maximum likelihood decoding parity check codes AWGN channels extrinsic information transfer EXIT function mutual information iterative decoding scheme binary memoryless symmetric channel BMS block code map decoder low density parity-check code LDPC code AWGN channel low density parity check codes AWGN channels Block codes maximum likelihood decoding memoryless systems parity check codes Iterative decoding Information Transfer decoders

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Iterative Decoding on Soft Information for Virtual Layered Space-Frequency Receivers

Iterative Decoding on Soft Information for Virtual Layered S...

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4th International Conference on Signal Processing and Communication Systems (ICSPCS)/12th International Symposium on DSP and Communication Systems (DSPCS)/9th Workshop on the Internet, Telecommunications and Signal Processing (WTSP)

作者： Imamura, Jun Denno, Satoshi Umehara, Daisuke Morikura, Masahiro Kyoto Univ Grad Sch Informat Sakyo Ku Kyoto 6068501 Japan

ISBN: (纸本)9781424479078

In this paper, we propose an iteration scheme for the virtual layered space frequency communication architecture. The architecture enables the decoding of the transmitted orthogonal frequency division multiplexing (OFDM)-QPSK signals even if the number of spatial multiplexed layers is twice that of receiving antennas over multipath fading channels. In the proposed iteration scheme, the map decoder and detector exchange soft information on the virtual channel. Using the soft informations, the architecture achieves much higher performance with lower computational complexity compared to maximum likelihood detection (MLD) even when the punctured code is used. Consequently, a gain of 4.5 dB can be achieved at a BER of 10-3 compared to that achieved with the MLD in the 4 x 2 MIMO-OFDM system when the rate 3/4 punctured code is used. The performance of the proposed architecture is verified by carrying out computer simulations.

关键词： BER map decoder MIMO-OFDM system OFDM modulation OFDM-QPSK signals computational complexity computational complexity computer simulations detector exchange soft information fading channels gain 4.5 dB iterative decoding iterative decoding maximum likeliho

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Mismatched Source Transition Probability Matrix for Adaptive map Decoding in MPEG-4 Imagery Wireless Transmission Systems

Mismatched Source Transition Probability Matrix for Adaptive...

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20th IEEE Symposium on Personal, Indoor and Mobile Radio Communications

作者： Mahapakulchai, Srijidtra Charoenlarpnopparut, Chalie Hasajitto, Siriwat Kasetsart Univ Dept Elect Engn Bangkok Thailand Thammasat Univ Sch Informat Sirindhom Int Inst Tech Comp & Commun Tech Bangkok Thailand

ISBN: (纸本)9781424451234

Here, we design the efficient technique of transmitting the source transition probability matrix (STPM) by accompanied with the lowest frequency subband (LFS). The entries of this stochastic matrix are adaptively computed by applying the first order Markov model with MPEG-4 zerotree sequences. Because of channel disturbances, we obtain the mismatched STPM at the ML-Viterbi receiver and then employ it for newly computed branch metrics at the map source-controlled channel decoder. For analysis, we also evaluate the residual redundancies for both the "Lena" and the "Barbara" images. The system performance is summarized in term of both PSNR (dB) and WER for three types of slow flat Rician fading channels. In the mismatched STPM simulation results, we still obtain the most PSNR improvement of about 0.14 dB.

关键词： Joint source-channel coding map decoder Markov model Residual redundancy Ring convolutional codes Rician fading channels

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Optimized DC-free Turbo coding scheme under the map decoding algorithm

Optimized DC-free Turbo coding scheme under the MAP decoding...

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Canadian Conference on Electrical and Computer Engineering

作者： Refaey, Ahmed Mokhtar, A. M. R. Fortier, Paul Univ Laval Dept Elect & Comp Engn Quebec City PQ G1K 7P4 Canada Univ Alexandria Dept Elect Engn Alexandria Egypt

ISBN: (纸本)9781424416424

A useful tool in the design of reliable digital communication systems is channel coding. Turbo codes have been shown to yield an outstanding coding gain close to theoretical limits in the additive white Gaussian noise (AWGN) channel. In this paper, we applied Wadayama's schemes of the direct current DC-free codes in a cascaded structure with turbo codes under the Maximum a Posteriori (map) decoding algorithm. The work done by Deng and Herro [1] impose relatively strong restrictions on the decomposition of the codeword. Wadayama removed such restrictions to treat any decomposition of the codeword. This is the main difference between the two approaches and it is why we used Wadayama's. The proposed scheme achieves the DC-free coding and error-correcting capability simultaneously. A given sequence becomes DC-free if and only if the absolute Running Digital Sum (RDS) value of the sequence is bounded by a constant for any time instant. The RDS control encoder generates a sequence giving the turbo coded sequence a bounded RDS value which results in a high error correcting capability. The high performances in terms of Bit Error Rate (BER) which is very close to the Shannon limits of this simple cascaded structure allows us to expect a new results with other capacity approaching EC block codes, such as low density parity check codes.

关键词： error control codes DC-free codes convolutional codes Turbo codes map decoder

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Throughput improvement of adaptive modulation system with optimal turbo coded V-BLAST technique using a STD scheme

Throughput improvement of adaptive modulation system with op...

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6th International Conference on Information, Communications and Signal Processing

作者： Lee, Kyunghwan Ryoo, Sangjin Hong, Daeki Yoo, Cheolwoo Yoon, Gilsang Cho, Insik Hwang, Intae Chonnam Natl Univ Dept Elect & Comp Engn 300 Yongbongdong Kwangju 500757 South Korea Sangmyung Univ Dept Informat & Telecomm Engn Seoul 330720 South Korea Myongji Univ Dept Commun Engn Seoul 449728 South Korea

ISBN: (纸本)9781424409822

In this paper, we propose and analyze an Adaptive Modulation System with optimal Turbo Coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique that adopts the extrinsic information from map (Maximum A Posteriori) decoder with Iterative Decoding as a prioiri probability in two decoding procedure of V-BLAST scheme;the ordering and the slicing. Also, comparing with the Adaptive Modulation System using conventional Turbo Coded V-BLAST technique that Is simply combined V-BLAST scheme with Turbo Coding scheme, we observe how much throughput performance can be improved. In addition, we apply a STD (Selection Transmit Diversity) scheme to the systems for more performance improvement. The results show that the proposed system applying a STD scheme gains about 1.77 Mbps at 11 dB SNR (Signal to Noise Ratio) compared to the conventional system using 2 transmit and 2 receive antennas.

关键词： AMC turbo code V-BLAST map decoder iterative decoding

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A turbo decoder architecture with scalable parallelism

A turbo decoder architecture with scalable parallelism

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IEEE Workshop on Signal Processing Systems Design and Implementation

作者： Engin, N Philips Res Labs Eindhoven Netherlands

ISBN: (纸本)0780385047

A scalable, programmable turbo decoder architecture is presented in this paper. The starting point is a comparison of the existing techniques on basis of scalability, area and power consumption. The results from these comparisons lead to a hybrid technique on which our architecture concept is based. The architecture is consisting of clusters each of which is a VLIW architecture. The upsizing is possible by adding a cluster and dividing the two data memories in banks. The window size is chosen according to the number of banks to prevent the conflicts. At the end of the paper, a short evaluation of the architecture is presented.

关键词： iterative decoding convolutional codes maximum likelihood decoding turbo codes parallel architectures programmable circuits convolutional decoders map decoder turbo decoder architecture scalable parallelism programmable turbo decoder scalability VLIW architecture clusters data memory banks data window size Iterative decoding Scalability programmable circuits Window Size maximum likelihood decoding Parallel architectures convolutional coding turbo codes ARCHITECTURE Building construction VLIW architecture Turbo Worm gears decoders

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