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Rapid Prototyping for Design and Test of FPGA-Based Model Predictive Controllers for Power Converters

JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2025年第4期20卷 2419-2438页

作者： Purraji, Marziye Zamiri, Elyas Sanchez, Alberto de Castro, Angel Univ Autonoma Madrid HCTLab Res Grp Calle Francisco Tomas & Valiente 11 Madrid 28049 Spain

Recent advancements in FPGA technology have made these devices a cost-effective alternative for implementing Model Predictive Controllers (MPCs). This paper addresses the fast prototyping of FPGA-based Finite Control Set (FCS)-MPCs and the essential verification process preceding hardware-level testing. The methodology leverages matlab hdl coder for automated hdl code generation. This approach offers a streamlined process and eliminates the need for expertise in hand-coded hdl, making it an ideal solution for power electronics engineers. The approach is exemplified using a three-phase active neutral point clamped converter. Beyond presenting the design approach, the paper introduces a systematic multi-stage verification process essential for the rapid prototyping of FCS-MPC controllers. This verification involves step-by-step simulations followed by experimental hardware-in-the-loop tests, ensuring the reliability of each stage for the smooth transition from pure simulation to FPGA hardware implementation of the controller. The proposed methodology not only simplifies the implementation and testing of the MPC algorithm within an FPGA but also facilitates the debugging process, a crucial aspect of the design phase.

关键词： FPGA Model predictive control Finite control set matlab hdl coder Power electronics

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Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis

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WIRELESS PERSONAL COMMUNICATIONS 2022年第3期127卷 1869-1878页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using matlab and Simulink and code generated using hdl coder from Math-Works. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. matlab hdl coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in matlab. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.

关键词： Hardware description language Register transfer language Field-programmable gate array High-level synthesis DSP filter Vivado matlab hdl coder

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Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2021年第6期40卷 2883-2894页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the matlab hardware description language (hdl) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of hdl designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of hdl Verifier and matlab. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

关键词： Hardware description language (hdl) High-level synthesis (HLS) Field programmable gate array (FPGA) Software-defined radio Vivado HLS matlab hdl coder

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High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications

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COMPUTATIONAL INTELLIGENCE 2021年第3期37卷 1056-1067页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial intelligence and machine learning applications require image processing algorithms running in real time on hardware systems like field-programmable gate array (FPGAs). They typically require high throughput to match real-time speeds and since they run alongside other processing algorithms, they are required to be area efficient as well. This article proposes a high-speed and low-area implementation of the Sobel edge detection algorithm. We created the design using a novel high-level synthesis (HLS) design method based on application specific bit widths for intermediate data nodes. Register transfer level code was generated using matlab hardware description language (hdl) coder for HLS. The generated hdl code was implemented on Xilinx Kintex 7 field programmable gate array (FPGA) using Xilinx Vivado software. Our implementation results are superior to those obtained for similar implementations using the vendor library block sets as well as those obtained by other researchers using similar implementations in the recent past in terms of area and speed. We tested our algorithm on Kintex 7 using real-time input video with a frame resolution of 1920 x 1080. We also verified the functional simulation results with a golden matlab implementation using FPGA in the loop feature of hdl Verifier. In addition, we propose a generic area, speed, and power improvement methodology for different HLS tools and application designs.

关键词： field-programmable gate array hardware description language high-level synthesis matlab hdl coder register transfer language Sobel edge detection Vivado

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Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation 4

Verification of Hardware Resource Utilization through High L...

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4th IEEE Global Conference for Advancement in Technology, GCAT 2023

作者： Pandey, Jyoti Asati, Abhijit R. Shenoy, Meetha V. Sikka, Prateek Rajasthan Pilani India STMicroelectronics India

ISBN: (纸本)9798350305258

Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory bandwidth. For optimized hardware deployment, which necessitates thorough optimization of system architectures and algorithms to get particularly efficient designs, a target system's hardware resources and an estimation of its performance at a greater degree of abstraction are crucial. Since the programmable hardware fabric may be customized for each unique network, Field Programmable Gate Arrays (FPGA) can accomplish this efficiency in this situation. This paper shows the high-level synthesis (HLS) of each of the different layers of optimized CNN using the matlab hdl coder. Along with its hdl resource utilization report, we also investigated the computational processes and hardware resource estimation of the previously developed optimized CNN. The hardware resources required by all the convolutional and fully connected layers of the optimized CNN matches exactly will the previously calculated resources. So, the hardware resource utilization is verified through HLS. The architecture takes fixed-point math into account. All layers are synthesized in Vivado 2022.2 with the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit as the target. © 2023 IEEE.

关键词： CNN Deep learning Hardware resource utilization High-level synthesis matlab hdl coder

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Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

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MICROPROCESSORS AND MICROSYSTEMS 2021年 80卷 103514-103514页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using matlab hdl coder for HLS. The generated hardware description language (hdl) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area (smaller gate count on target FPGA) and speed for the same target board.

关键词： Hardware description language Register transfer language Field-programmable gate array High-Level Synthesis Harris corner detection Vivado matlab hdl coder

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High-Level synthesis assisted design and verification framework for automotive radar processors

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MICROPROCESSORS AND MICROSYSTEMS 2020年 78卷 103259-103259页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

In radar-based advanced driver assistance systems, baseband processing is necessary to detect the speed, distance, and angle of elevation of the target (e.g., vehicle, pedestrian, traffic sign, etc.). The target and the source often move at high speeds;therefore, the computation rate must be sufficiently high to perform actions (e.g., braking) in real-time. Software-based implementations of such systems fall short of the required performance, which has led to an increase in the popularity of custom hardware implementations, e.g., on field-programmable gate arrays (FPGAs). FPGAs also serve as platforms to develop software concurrent with system-on-chip (SoC) development, thereby decreasing the time to market. High-level synthesis (HLS) tools are gaining considerable attention in the very-large-scale integration design community because of their flexibility. In this paper, we propose a novel design and verification framework for a RADAR processing SoC. The framework is assisted by an HLS-based design scheme for the processor and supports the application of a real-world stimulus to register transfer-level design implementation running on FPGAs. Customer use cases for the distance and velocity calculations are executed in a pre-silicon environment using range and Doppler processing on the Xilinx Kintex-7 (XC 7K 480T) FPGA. Our findings show that the proposed framework, based on matlab hdl coder and hdl Verifier, is superior to similar implementations from prior research in terms of speed and FPGA resources. This is owing to the usage of appropriate HLS directives and the usage of a novel design method based on applicationspecific bit width for intermediate data nodes.

关键词： Advanced driver assistance systems (ADAS) System on chip (SoC) Register transfer language (RTL) Field-programmable gate array (FPGA) High-level synthesis (HLS) matlab hdl coder matlab hdl Verifier

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