This paper proposes an improved max-log-maximum a posteriori (map) algorithm for turbo decoding and turbo equalization. The proposed algorithm utilizes the MacLaurin Series to expand the logarithmic term in the Jacobi...
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This paper proposes an improved max-log-maximum a posteriori (map) algorithm for turbo decoding and turbo equalization. The proposed algorithm utilizes the MacLaurin Series to expand the logarithmic term in the Jacobian logarithmic function of the log-mapalgorithm. In terms of complexity, the proposed algorithm can easily be implemented by means of adders and comparators as this is the case for the max-log-map algorithm. In addition, simulation results show that the proposed algorithm performs very closely to the log-mapalgorithm for both turbo decoding over additive-white-Gaussian-noise channels and turbo equalization over frequency-selective channels. Further, it is shown than even in a high-loss intersymbol-interference channel, the proposed algorithm preserves its performance close to that of the log-mapalgorithm, while there is a wide gap between the performance of the log-map and max-log-map turbo equalizers.
Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With t...
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ISBN:
(纸本)9781467365406
Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With the advent of FPGAs, the realization of the BCJR algorithm and different simplified versions of BCJR algorithm on hardware is possible. A VHDL implementation of Turbo decoder using the max-log-map algorithm has been discussed in this paper. The target device used for this implementation is Xilinx Virtex-6 FPGA. Simulation and synthesis were carried out using ModelSim SE 6.1 and Xilinx ISE 10.1. BER plots and input and output waveforms for interleaver, deinterleaver, max-log-map decoder and Turbo decoder are also presented.
The iterative decoding in turbo code has very high decoding complexity. This paper adopts the improved log-mapalgorithm for decoding of Space-Time Turbo Trellis Code (ST-Turbo TC) in the slow Rayleigh fading channels...
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The iterative decoding in turbo code has very high decoding complexity. This paper adopts the improved log-mapalgorithm for decoding of Space-Time Turbo Trellis Code (ST-Turbo TC) in the slow Rayleigh fading channels. Using the MacLaurin formulae, the proposed algorithm expands the logarithmic function of the log-map. It makes the computation much easier and the operation of the hardware system much faster. Simulation results show that the proposed algorithm performs very closely to the log-mapalgorithm for decoding of ST-Turbo TC in slow Rayleigh fading channels.
A parallelised max-log-map model (P-max-log-map) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed mo...
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A parallelised max-log-map model (P-max-log-map) that exploits the sub-word parallelism and very long instruction word architecture of a microprocessor or a digital signal processor (DSP) is presented. The proposed model reduces considerably the computational complexity of the max-log-map algorithm;and therefore facilitates easy implementation.
In this paper, we propose a simplified log-mapalgorithm that is equivalent to the log-mapalgorithm in terms of the bit-error-rate (BER) performance, but without its implementation difficulties. The proposed algorith...
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ISBN:
(纸本)9781424497898
In this paper, we propose a simplified log-mapalgorithm that is equivalent to the log-mapalgorithm in terms of the bit-error-rate (BER) performance, but without its implementation difficulties. The proposed algorithm is based on a linear approximation of the correction function in the log-mapalgorithm over different signal-to-noise ratio (SNR) regions. This approximation is simple to implement by avoiding the number of complicated operations. Simulation results demonstrate that this simplified algorithm can achieve the same BER performance as the log-mapalgorithm.
This paper describes two new matrix transform algorithms for the max-log-map decoding of turbo codes. In the proposed algorithms, the successive decoding procedures carried out in the conventional max-log-map algorith...
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ISBN:
(纸本)0780370805
This paper describes two new matrix transform algorithms for the max-log-map decoding of turbo codes. In the proposed algorithms, the successive decoding procedures carried out in the conventional max-log-map algorithm are performed in parallel, and well formulated into a set of simple and regular matrix operations, which can therefore considerably speed up the decoding operations and reduce the computational complexity. The matrix max-log-map algorithms also maintain the advantage of the general logarithmic map like algorithms in avoiding complex numerical representation problems. They particularly facilitate the implementations of the logarithmic map like algorithms in special-purpose parallel processing VLSI hardware architectures. The matrix algorithms also allow simple implementations by using shift registers. The proposed implementation architectures for the matrix max-log-map decoding can effectively reduce the memory capacity and simplify the data accesses and transfers required by the conventional max-log-map as well as mapalgorithms.
The rapid growth in wireless communication has caused an increased demand for high speed error control decoders with improved BER performance. Turbo codes, the Shannon limit approaching codes, use max-log-map decoders...
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ISBN:
(纸本)9781538646922
The rapid growth in wireless communication has caused an increased demand for high speed error control decoders with improved BER performance. Turbo codes, the Shannon limit approaching codes, use max-log-map decoders as the component decoders in the iterative decoding process. The demand for high speed error control decoders has led to an increased interest in the design of hardware-secure max-log-map decoders with high throughput and reduced area. This paper focuses on designing a high throughput max-log-map decoder with reduced area and analyzing the effect of a run time triggered multinet connected Trojan on its performance. High throughput is achieved by using radix-4 and radix-8 architectures and area is optimized using maximum sharing of resources (MSR) architec-ture. This architecture uses a modified add-compare-select unit designed by effectively utilizing the relationship existing between the branch metrics. Trojan analysis is performed by inserting a run time triggered multinet connected Trojan and comparing its performance with the Trojan free decoder.
This work addresses the problem of joint source-channel decoding of a Markov sequence which is first encoded by a source code, then encoded by a convolutional code, and sent through a noisy memoryless channel. It is s...
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This work addresses the problem of joint source-channel decoding of a Markov sequence which is first encoded by a source code, then encoded by a convolutional code, and sent through a noisy memoryless channel. It is shown that for Markov sources satisfying the so-called Monge property, both the maximum a posteriori probability (map) sequence decoding, as well as the soft output max-log-map decoding can be accelerated by a factor of K without compromising the optimality, where K is the size of the Markov source alphabet. The key to achieve a higher decoding speed is a convenient organization of computations at the decoder combined with a fast matrix search technique enabled by the Monge property. The same decrease in complexity follows, as a by-product of the development, for the soft output max-log-map joint source channel decoding in the case when the convolutional coder is absent, result which was not known previously.
In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consum...
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In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consumption in the turbo decoder. The main idea is based on re-encoding technique combined with dummy insertion during the iterative decoding process. This technique, named "toward zero path" (TZP) helps in reducing the state transition activity of the max-log-map algorithm by trying to maintain the survivor path on the 'zero path' of the trellis. The design of a turbo decoder based on the TZP technique, associated with different power reduction technique (saturation of state metrics, stoping criterium) is described. The resulting turbo decoder was implemented onto a Xilinx VirtexII-Pro field-programmable gate array (FPGA) in a digital communication experimental setup. Performance and accurate power dissipation measurements have been done thanks to dynamic partial reconfiguration of the FPGA device. The experimental results have shown the interest of the different contributions for the design of turbo decoders.
As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculati...
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As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the max-log-map algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-map, that results in a similar BER performance to the log-mapalgorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-map turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.
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