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A Unitable Computing Architecture for Chip Multiprocessors

COMPUTER JOURNAL 2011年第12期54卷 2033-2052页

作者： Chiu, Jih-Ching Chou, Yu-Liang Chen, Po-Kai Su, Ding-Siang Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung Taiwan

This paper proposes a unitable multi-core architecture, called hyperscalar, that can dynamically unite many scalar cores as a larger superscalar processor to accelerate a thread. To accomplish this, this paper proposes the virtual shared register files (VSRFs) that help the instructions of a thread in different cores can logically face a uniform set of register files. We also propose an instruction analyzer that can detect and tag the dependence information to the newly fetched instructions. With the tags, instructions in the united cores can issue requests to obtain their remote operands via the VSRF. Thus, the dependences arising among instructions in different cores can be resolved. Moreover, some extended instructions are defined for programmers to grow or shrink the number of united cores to match the available instruction level parallelism for different applications. The reconfigurable feature of hyperscalar covers a spectrum of workloads well, providing high single-thread performance when thread level parallelism (TLP) is low and high throughput when TLP is high. Simulation results show that the eight-core hyperscalar chip multiprocessor's two-, four-and eight-core-united configurations archive 93, 80 and 76% of the performance of the monolithic two-, four-and eight-issue out-of-order superscalar processors with lower area costs and better support for software diversity.

关键词： reconfigurable hardwares mimd processors dynamic multi-core superscalar CMP chip multiprocessors

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On-Chip Active Messages for Speed, Scalability, and Efficiency

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2015年第2期26卷 507-515页

作者： Harting, R. Curtis Dally, William J. Stanford Univ Dept Elect Engn Stanford CA 94305 USA Nvidia Santa Clara CA USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

This paper describes and quantifies the benefits of adding low-overhead active messages to many-core, cache-coherent chip-multiprocessors. The active messages we analyze are user defined and trigger the atomic execution of a custom software handler at the destination. Programmers can use these active messages to both move data with less overhead than cache coherency and, more importantly, explicitly send computation to data. Doing so greatly improves (11 x speed, 4.8 x energy) communication idioms such as shared object modification, reductions, data walks, point-to-point communication, and all-to-all communication. Active messages enhance program scalability: applications using them run 63 percent faster with 11 percent less energy on 256 cores. The relative benefits of active messages grow with larger numbers of cores.

关键词： Parallel architecture parallel processors mimd processors shared memory concurrent programming

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A hyperscalar dual-core architecture for embedded systems

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MICROprocessors AND MICROSYSTEMS 2013年第8期37卷 929-940页

作者： Chiu, Jih-Ching Yang, Kai-Ming Chou, Yu-Liang Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 804 Taiwan

This paper proposes a lightweight reconfigurable dual-core architecture for embedded systems, called hyperscalar dual-core architecture. The proposed architecture can play three different roles (a 2-issue statically scheduled superscalar processor, a homogeneous dual-core processor, or a standalone single-core processor), allowing embedded systems to accommodate diverse workloads. The proposed design uses four extended instructions to enable programmers to dynamically switch the roles of the proposed architecture. This paper also presents an instruction analyzer (IA) that connects two scalar in-order cores to handle role switching. The design of IA makes it possible for the two cores to work together like a 2-issue statically scheduled superscalar processor. Based on the proposed dispatching rules, the IA dispatches instructions with data dependencies to the same core. Since two cores act like a statically scheduled superscalar processor, they can resolve data dependencies using existing forwarding paths without introducing the high-area-cost inter-core operand-switching crossbars. Simulation results show that when the proposed architecture works in a statically scheduled superscalar manner, it achieves a 26% higher instructions per cycle (IPC) averaged across all 29 benchmarks from the MiBench suite than a scalar in-order core. The increases in area and power to extend a homogeneous dual-core processor to a hyperscalar dual-core processor are only 1.8% and 1.75%, respectively, using 90 nm CMOS technology. (C) 2012 Elsevier B.V. All rights reserved.

关键词： Reconfigurable hardwares mimd processors Dynamic multi-core Superscalar CMP Chip multiprocessors

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On-chip interconnection architecture of the tile processor

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IEEE MICRO 2007年第5期27卷 15-31页

作者： Wentzlaff, David Griffin, Patrick Hoffmann, Henry Bao, Liewei Edwards, Bruce Ramey, Carl Mattina, Matthew Miao, Chyi-Chang Brown, John F., III Agarwal, Anant Massachusetts Inst. of Technol Cambridge

Imesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2d mesh networks, each specialized for a different use. Taking advantage of the five networks, the cbased ilib interconnection library efficiently maps program communication across the on-chip interconnect. The tile processor's first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

关键词： Network On Chip Computer Architecture Multiprocessor Interconnection Networks C Based ILIB Interconnection Library Onchip Interconnection Architecture Tile Processor 2 D Mesh Network Network On A Chip Bandwidth Multicore Processing Mesh Networks Computer Architecture Communication Networks Hardware Multiprocessor Interconnection Networks Parallel Architectures mimd processors On Chip Interconnection Networks Multicore Architectures Mesh Networks

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PITON: A MANYCORE PROCESSOR FOR MULTITENANT CLOUDS

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IEEE MICRO 2017年第2期37卷 70-80页

作者： McKeown, Michael Fu, Yaosheng Tri Nguyen Zhou, Yanqi Balkind, Jonathan Lavrov, Alexey Shahrad, Mohammad Payne, Samuel Wentzlaff, David Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Princeton Univ Princeton NJ 08544 USA

PITON IS A 25-CORE MANYCORE PROCESSOR THAT REIMAGINES THE DATACENTER ARCHITECTURE, BREAKING DOWN BARRIERS BETWEEN CHIPS, NODES, AND RACKS, AND ENABLING FLEXIBILITY, PERFORMANCE, AND ENERGY EFFICIENCY AT SCALE. IT IS DESIGNED NOT ONLY AS A SINGLE CHIP, BUT AS A LARGE-SCALE SYSTEM. PITON SUPPORTS SHARED MEMORY ACROSS ARBITRARY CORES IN THE SYSTEM AND IS TAILORED TO INFRASTRUCTURE-AS-A-SERVICE CLOUDS.

关键词： Cloud Computing Data Centers Computer Architecture Energy Efficiency Bandwidth Large Scale Systems Multiprocessing Systems Microprocessors Low Power Design mimd processors Parallel processors Multithreaded processors Multicore Single Chip Multiprocessors On Chip Interconnection Networks Processor Architectures Servers Multiprocessor Systems Cloud Computing

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TOP-DOWN STRUCTURED PARALLELIZATION OF EMBEDDED IMAGE-PROCESSING APPLICATIONS

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IEE PROCEEDINGS-VISION IMAGE AND SIGNAL PROCESSING 1994年第6期141卷 431-437页

作者： DOWNTON, AC TREGIDGO, RWS CUHADAR, A Dept. of Electron. Syst. Eng. Essex Univ. Colchester UK

The authors present a general system design method which is intended to support parallelisation of complete image processing applications using mimd processors. The approach is based upon the utilisation of a generic system level parallel processor architecture, the 'pipeline processor farm' (PPF), and is applicable to any embedded application with continuous input/output. The design method is illustrated using applications from the fields of computer vision and image coding. The design model accommodates several commonly exploited parallel processing paradigms, maps conveniently to the software structure of most image processing algorithms, provides incrementally scalable performance, and enables upper-bound speedups to be easily estimated from profiling data generated by the original sequential implementation of the application. It is believed that the approach has significant application in parallel embedded systems design, in the development environment, and in simulation work for computationally intensive image coding algorithms.

关键词： IMAGE PROCESSING mimd processors PARALLEL PROCESSING EMBEDDED SYSTEMS

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THE ETH-MULTIPROCESSOR EMPRESS - A DYNAMICALLY CONFIGURABLE mimd SYSTEM

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IEEE TRANSACTIONS ON COMPUTERS 1982年第11期31卷 1035-1044页

作者： BUEHRER, RE BRUNDIERS, HJ BENZ, H BRON, B FRIESS, H HAELG, W HALIN, HJ ISACSON, A TADIAN, M Swiss Federal Institute of Technology ETH

The mimd multiprocessor EMPRESS (ETH-Multiprocessor) to be described was built in order to study the performance of mimd architectures in general, and particularly in the field of simulation problems. By means of a dynamically configurable architecture in combination with a powerful processor intercommunication principle, the system is able to handle two-stage parallelism: several independent subtasks with inherent parallelism can be run simultaneously. This concept incorporates features of a quite general nature allowing in principle the implementation of other software.

关键词： PSCSP Computer Architecture Digital Simulation Dynamic Architecture EMPRESS mimd processors Parallel Computation Parallel processors

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AsAP: A fine-grained many-core platform for DSP applications

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IEEE MICRO 2007年第2期27卷 34-45页

作者： Baas, Bevan Yu, Zhiyi Meeuwsen, Michael Sattari, Omar Apperson, Ryan Work, Eric Webb, Jeremy Lai, Michael Mohsenin, Tinoosh Truong, Dean Cheung, Jason Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

Many emerging and future applications require significant levels of complex digital signal processing and operate within limited power budgets. Moreover, dramatically rising VLSI fabrication and design costs make programmable and reconfigurable solutions increasingly attractive. The AsAP project addresses these challenges with a chip multiprocessor composed of simple processors with small memories, achieving high energy efficiency and throughput in a small chip area.

关键词： Microarchitecture Multiprocessors mimd processors Embedded Systems Special Purpose And Application Based Systems Digital Signal Processing GALS Networking

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The Performance Prediction and Improvement of SPH with the Interaction-List-Sharing Method on PEZY-SCs 19th

The Performance Prediction and Improvement of SPH with the I...

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19th Annual International Conference on Computational Science (ICCS)

作者： Hosono, Natsuki Furuichi, Mikito Japan Agcy Marine Earth Sci & Technol Kanazawa Ku 3173-25 Showa Machi Yokohama Kanagawa 2360001 Japan RIKEN Ctr Computat Sci Chuo Ku 7-1-26 Minatojima Minami Machi Kobe Hyogo 6500047 Japan

ISBN: (纸本)9783030227500;9783030227494

The demands for the optimization of particle-based methods with short-range interaction forces such as those in smoothed particle hydrodynamics (SPH) is increasing, especially for many-core architectures. However, because particle-based methods require large amount of memory access, it is challenging to obtain high efficiency for low-byte/FLOP many-core architectures. Hence, an efficient technique, the so-called "multiwalk" method, was developed in an N-body gravitational field. The key of the multiwalk method is in sharing of the interaction lists with multiple particles to offer an efficient use of the cache memory in the double-loops operation for calculating the interactions and reducing the main memory access. However, such performance improvement is not clear for the problems with short-range interaction forces such as those in SPH. In this paper, we proposed a theoretical performance model to examine the tradeoff relations between the memory and the cost of floating point operations to optimise the SPH code. We also validated the model with the wall-clock time spent on the PEZY-SCs (SC1 and SC2).

关键词： mimd processors Smoothed particle hydrodynamics

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AsAP: A fine-grained many-core platform for DSP applications

AsAP: A fine-grained many-core platform for DSP applications

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Hot Chips 18 Conference

关键词： Digital signal processing Embedded systems GALS networking Microarchitecture mimd processors Multiprocessors Special-purpose and application-based systems

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