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New Hardware Architectures for Montgomery Modular Multiplication algorithm

IEEE TRANSACTIONS ON COMPUTERS 2011年第7期60卷 923-936页

作者： Huang, Miaoqing Gaj, Kris El-Ghazawi, Tarek 1 Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA

Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koc proposed the Multiple-Word Radix-2 Montgomery Multiplication (mwr2mm) algorithm and introduced a now-classic architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper, we propose two new hardware architectures that are able to perform the same operation in approximately n clock cycles with almost the same clock period. These two architectures are based on precomputing partial results using two possible assumptions regarding the most significant bit of the previous word. These two architectures outperform the original architecture of Tenca and Koc, in terms of the product latency times area by 23 and 50 percent, respectively, for several most common operand sizes used in cryptography. The architecture in radix-2 can be extended to the case of radix-4, while preserving a factor of two speedup over the corresponding radix-4 design by Tenca, Todorov, and Koc from CHES 2001. Our optimization has been verified by modeling it using Verilog-HDL, implementing it on Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

关键词： Montgomery multiplication mwr2mm algorithm hardware optimization field-programmable gate arrays

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An optimized hardware architecture for the Montgomery multiplication algorithm

引用

11th International Workshop on Practice and Theory in Public Key Cryptography

作者： Huang, Miaoqing Gaj, Kris Kwon, Soonhak El-Ghazawi, Tarek George Washington Univ Washington DC 20052 USA George Mason Univ Fairfax VA 22030 USA Sungkyunkwan Univ Suwon 440746 South Korea

ISBN: (纸本)9783540784395

Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koc introduced a now-classical architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper we propose and discuss an optimized hardware architecture performing the same operation in approximately n clock cycles with almost the same clock period. Our architecture is based on pre-computing partial results using two possible assumptions regarding the most significant bit of the previous word, and is only marginally more demanding in terms of the circuit area. The new radix-2 architecture can be extended for the case of radix-4, while preserving a factor of two speed-up over the corresponding radix-4 design by Tenca, Todorov, and Kog from CHES 2001. Our architecture has been verified by modeling it in Verilog-HDL, implementing it using Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

关键词： Montgomery multiplication mwr2mm algorithm field programmable gate arrays

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