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The Reflective Milawa Theorem Prover is Sound (Down to the machine code that Runs it)

JOURNAL OF AUTOMATED REASONING 2015年第2期55卷 117-183页

作者： Davis, Jared Myreen, Magnus O. Centaur Technol Inc Austin TX USA Chalmers Univ Technol CSE Dept S-41296 Gothenburg Sweden Univ Cambridge Comp Lab Cambridge CB2 3QG England

This paper presents, we believe, the most comprehensive evidence of a theorem prover's soundness to date. Our subject is the Milawa theorem prover. We present evidence of its soundness down to the machine code. Milawa is a theorem prover styled after NQTHM and ACL2. It is based on an idealised version of ACL2' s computational logic and provides the user with high-level tactics similar to ACL2' s. In contrast to NQTHM and ACL2, Milawa has a small kernel that is somewhat like an LCF-style system. We explain how the Milawa theorem prover is constructed as a sequence of reflective extensions from its kernel. The kernel establishes the soundness of these extensions during Milawa's boot-strapping process. Going deeper, we explain how we have shown that the Milawa kernel is sound using the HOL4 theorem prover. In HOL4, we have formalized its logic, proved the logic sound, and proved that the source code for the Milawa kernel (1,700 lines of Lisp) faithfully implements this logic. Going even further, we have combined these results with the x86 machine-code level verification of the Lisp runtime Jitawa. Our top-level theorem states that Milawa can never claim to prove anything that is false when it is run on this Lisp runtime.

关键词： Soundness Theorem proving Proof assistant machine code

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Evolving GPU machine code

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JOURNAL OF machine LEARNING RESEARCH 2015年第1期16卷 673-712页

作者： da Silva, Cleomar Pereira Dias, Douglas Mota Bentes, Cristiana Cavalcanti Pacheco, Marco Aurelio Cupertino, Leandro Fontoura Pontif Catholic Univ Rio de Janeiro PUC Rio Dept Elect Engn BR-22451900 Rio De Janeiro RJ Brazil Fed Inst Educ Sci & Technol Catarinense IFC Dept Educ Dev BR-89560000 Videira SC Brazil State Univ Rio de Janeiro UERJ Dept Syst Engn BR-20550013 Rio De Janeiro RJ Brazil Univ Toulouse Toulouse Inst Comp Sci Res IRIT F-31062 Toulouse 9 France

Parallel Graphics Processing Unit (GPU) implementations of GP have appeared in the literature using three main methodologies: (i) compilation, which generates the individuals in GPU code and requires compilation;(ii) pseudo-assembly, which generates the individuals in an intermediary assembly code and also requires compilation;and (iii) interpretation, which interprets the codes. This paper proposes a new methodology that uses the concepts of quantum computing and directly handles the GPU machine code instructions. Our methodology utilizes a probabilistic representation of an individual to improve the global search capability. In addition, the evolution in machine code eliminates both the overhead of compiling the code and the cost of parsing the program during evaluation. We obtained up to 2.74 trillion GP operations per second for the 20-bit Boolean Multiplexer benchmark. We also compared our approach with the other three GPU-based acceleration methodologies implemented for quantum-inspired linear GP. Significant gains in performance were obtained.

关键词： genetic programming graphics processing units machine code

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Development and implementation of a software for wire arc additive manufacturing preprocessing planning: trajectory planning and machine code generation

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WELDING IN THE WORLD 2022年第3期66卷 455-470页

作者： Ferreira, Rafael Pereira Vilarinho, Louriel Oliveira Scotti, Americo Fed Inst Educ Sci & Technol Maranhao IFMA Campus Barra do Corda Barra Do Corda MA Brazil Fed Univ Uberlandia UFU Ctr Res & Dev Welding Proc Laprosolda Uberlandia MG Brazil Univ West UW Dept Engn Sci Div Welding Technol Trollhattan Vastra Gotaland Sweden

To overcome a shortage of flexible and low-cost solutions for wire arc additive manufacturing (WAAM) preprocessing, this work's objective was to develop and validate an in-house computational programme in an open-source environment for WAAM preprocessing planning. Algorithms for reading STL (stereolithography) files and implementing rotation, slicing, trajectory planning, and machine code generation were elaborated and implemented in the Scilab environment (free and open-source). A graphical interface was developed to facilitate user interaction, with 5 options for path planning. The functionality of each work step is detailed. For validation of the software, single and multiple-layer prints, with different geometrical complexity and printing challenges, were built in a CNC table geared by the generated machine code. The validation criteria were deposition imperfection, morphological, and dimensional tolerances. The outputs showed that the parts were successfully printed. Therefore, this work demonstrates that Scilab provides the necessary resources for companies and universities to implement and/or develop algorithms for planning and generating trajectories for WAAM. Moreover, emerging ideas can be reasonably easily implemented in such software, not always possible in commercial packages.

关键词： Wire arc additive manufacturing (WAAM) Preprocessing planning Trajectory generation machine code G-code Open-source code programming

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Efficient and Precise Information Flow Control for machine code through Demand-Driven Secure Multi-Execution 19

Efficient and Precise Information Flow Control for Machine C...

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9th ACM Conference on Data and Application Security and Privacy (CODASPY)

作者： Pfeffer, Tobias Goethel, Thomas Glesner, Sabine Tech Univ Berlin Berlin Germany

ISBN: (纸本)9781450360999

Dynamic Information Flow Control (IFC) systems, like No-Sensitive-Upgrade or Permissive-Upgrade, can guarantee Termination-Insensitive Non-Interference, but reject valid programs due to their inability to track implicit flows. More advanced multi-execution based approaches, like Shadow Execution and Secure Multi-Execution, are precise and guarantee Termination-Sensitive Non-Interference, but require additional resources or, in the case of Faceted Evaluation, deep changes to the execution semantics. In this paper, we propose a novel efficient and precise Information Flow Control system for machine code through Demand-Driven Secure Multi-Execution. Our key idea is to use lightweight single-execution monitoring as long as the execution is secretless and fork multiple copies on-demand when necessary. We present the first Secure Multi-Execution implementation for legacy code in Unix-based environments and show that our demand-driven optimization drastically reduces the run-time overhead for cat and sha256sum. Our results indicate that further acceleration is possible through improved static analyses, making multi-execution based IFC systems applicable to machine code.

关键词： Information Flow Control machine code Multi-Execution

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Verification of Concurrent machine code Running on a Single-Core machine 24

Verification of Concurrent Machine Code Running on a Single-...

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39th Annual ACM Symposium on Applied Computing (SAC)

作者： Khakpour, Narges Newcastle Univ Newcastle Upon Tyne Tyne & Wear England

ISBN: (纸本)9798400702433

In this paper, we propose a machine-independent logic to verify concurrent machine code running on a single-core machine, using a combination of separation logic and rely/guarantee reasoning. Separation logic is employed to reason about local resources, and rely/guarantee reasoning is used to analyze the shared state. We formalize and prove the soundness of this logic. To illustrate the applicability of the logic in realistic platforms, we instantiate it with ARMv7 architecture and apply the instantiated logic to verify a UART driver in the presence of interrupts.

关键词： machine code Formal Verification Hoar Logic Assume-Guarantee Reasoning

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Static Analysis of machine code for Supply-Chain Risk Management

Static Analysis of Machine Code for Supply-Chain Risk Manage...

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13th IEEE International Conference on Technologies for Homeland Security (HST)

作者： Anderson, Paul Loginov, Alexey GrammaTech Inc Ithaca NY 14850 USA

ISBN: (纸本)9781479915354;9781479939633

This paper discusses the product-oriented approach to software supply-chain risk management: a determination of the trustworthiness of software applications, or the relative trustworthiness among a set of software applications, based on automated analysis and inspection of their actual binary machine codes. The system, named codeSonar T for binaries, is a static-analysis tool that can find security vulnerabilities in stripped and optimized executables. It is built as an extension to a successful product for analyzing source code, so it is also capable of analyzing source and machine code simultaneously. It can find defects such as buffer overruns, null pointer dereferences, resource leaks, and uninitialized variables.

关键词： component static analysis security vulnerabilities machine code supply-chain risk management

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Partial Evaluation of machine code 2015

Partial Evaluation of Machine Code

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ACM SIGPLAN International Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA)

作者： Srinivasan, Venkatesh Reps, Thomas Univ Wisconsin Madison Madison WI 53706 USA GrammaTech Inc Ithaca NY 14850 USA

ISBN: (纸本)9781450336895

This paper presents an algorithm for off-line partial evaluation of machine code. The algorithm follows the classical two-phase approach of binding-time analysis (BTA) followed by specialization. However, machine-code partial evaluation presents a number of new challenges, and it was necessary to devise new techniques for use in each phase. Our BTA algorithm makes use of an instruction-rewriting method that "decouples" multiple updates performed by a single instruction. This method counters the cascading imprecision that would otherwise occur with a more naive approach to BTA. Our specializer specializes an explicit representation of the semantics of an instruction, and emits residual code via machine-code synthesis. Moreover, to create code that allows the stack and heap to be at different positions at run-time than at specialization-time, the specializer represents specialization-time addresses using symbolic constants, and uses a symbolic state for specialization. Our experiments show that our algorithm can be used to specialize binaries with respect to commonly used inputs to produce faster binaries, as well as to extract an executable component from a bloated binary.

关键词： Partial evaluation machine code BTA specialization machine-code synthesis IA-32 instruction set

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Testing of Utilities for Finding Vulnerabilities in the machine code of Telecommunication Devices 19

Testing of Utilities for Finding Vulnerabilities in the Mach...

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19th International Conference on Advanced Communication Technology (ICACT)

作者： Buinevich, Mikhail Izrailov, Konstantin Vladyko, Andrei Bonch Bruevich St Petersburg State Univ Telecommu 22-1 Prospekt Bolshevikov St Petersburg Russia

ISBN: (纸本)9788996865094

The article is devoted to the authors' machine code algorithmization utility to find vulnerabilities in telecommunication devices. The utility is compared with its closest analogue the IDA Pro software and its plug-in - Hex-Rays. The paper presents the key tests that are used for such comparison and the results of software tools operation for them. The formalized outcome of the comparative analysis justifies the advantages of the authors' utility for solving this task.

关键词： vulnerability machine code algorithmization IDA Pro utility testing

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Control Your Trs 80 Better Basic and machine code

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2016年

作者： ian aut 2 stewart

Control Your Trs 80 Better Basic and machine code by Stewart, Ian Aut (De-101)107887932; Jones, Robin Aut (De-101)110098676; Scrimshaw, Nevin B. Aut (De-101)110148088; published by Boston Basel Stuttgart Birkhäuser

关键词： array basic better carry flag code control data structure french countdown gosub goto loop machine machine code machine language main program maschinensprache print program routine sign flag start address tail pointer trs 80 waiting time

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An Improved Algorithm for Slicing machine code

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ACM SIGPLAN NOTICES 2016年第10期51卷 378-393页

作者： Srinivasan, Venkatesh Reps, Thomas Univ Wisconsin Madison WI 53706 USA GrammaTech Inc Ithaca NY USA

machine-code slicing is an important primitive for building binary analysis and rewriting tools, such as taint trackers, fault localizers, and partial evaluators. However, it is not easy to create a machine-code slicer that exhibits a high level of precision. Moreover, the problem of creating such a tool is compounded by the fact that a small amount of local imprecision can be amplified via cascade effects. Most instructions in instruction sets such as Intel's IA-32 and ARM are multi-assignments: they have several inputs and several outputs (registers, flags, and memory locations). This aspect of the instruction set introduces a granularity issue during slicing: there are often instructions at which we would like the slice to include only a subset of the instruction's semantics, whereas the slice is forced to include the entire instruction. Consequently, the slice computed by stateof- the-art tools is very imprecise, often including essentially the entire program. This paper presents an algorithm to slice machine code more accurately. To counter the granularity issue, our algorithm performs slicing at the microcode level, instead of the instruction level, and obtains a more precise microcode slice. To reconstitute a machine-code program from a microcode slice, our algorithm uses machine-code synthesis. Our experiments on IA-32 binaries of FreeBSD utilities show that, in comparison to slices computed by a state-of-the-art tool, our algorithm reduces the size of backward slices by 33%, and forward slices by 70%.

关键词： Program slicing machine code microcode-level SDG granularity issue program reconstitution machine-code synthesis IA-32 instruction set

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